ENEE 350: Computer Organization
—
Project 4 (10%): Cache Organization
1
Project 4 (10%): Cache Organization
ENEE 350: Computer Organization, Spring 2001
Assigned: Wednesday, April 25; Due: Wednesday, May 9
Purpose
This project is intended to help you understand in detail how
caches
work by building a cache
model that processes an
address trace
. This project also returns to the topic of performance mea-
surement, so your simulator will also keep track of performance numbers and support different
design options. For instance, your program should support caches of different sizes, block sizes,
and associativities. Your simulator must maintain statistics during execution to report perfor-
mance numbers when it finishes processing the address trace.
1. Problem
You will implement a cache system that emulates either a
Harvard architecture
(separate instruc-
tion and data caches, also called a
split cache architecture
) or a
unified architecture
(one big cache
that holds both instructions and data). The choice will be made on the command line. All caches
should be
write-through, write-allocate
. All associative caches will use an
NMRU
replacement
policy: to replace a block, keep track of the most recently used block in the set, and choose among
the remaining blocks randomly. Note that only applies to data caches, since you cannot explicitly
write to an instruction cache. The cache
size
should be variable, as should the cache’s
blocksize
and the cache’s
associativity
; these will be variables passed in on the command-line.
You are to keep statistics on the following event types:
•
instruction and data cache references
•
instruction and data cache misses and miss rates
•
total cycles required to execute program (assuming a 1-cycle hit and a 100-cycle miss)
Output these at the end of the simulator’s execution, using the provided
printStats
function.
2. Address Traces
An
address trace
represents the dynamic behavior of a program. Typically, an address trace is a
stream of data items, each of which contains the informaiton for one instruction. Here is an exam-
ple stream:
1070016
32832 0 14894476
2129920 1 14894545
1900288
1859360
1403456
1403520 0 14900052
1479936 0 14901872
1408128 0 14903660
2456704 0 14903729
826560 1 14904253
1411392
The first column represents the address of the instruction (the program counter), the next column
represents whether the instruction is a read (0) or a write (1), and the last column represents the
data address that the instruction reads or writes. If a line does not have an entry in columns 2 and
3, then it is not a load/store instruction, and it therefore only references the instruction cache.
