Computer design – an application of digital logic design procedures
Computer = processing unit + memory system
Processing unit = control + datapath
Control = finite state machine
inputs = machine instruction, datapathconditions
outputs = register transfer control signals, ALU operation codes
instruction interpretation = instruction fetch, decode, execute
Datapath = functional units + registers
functional units = ALU, multipliers, dividers, etc.
registers = program counter, shifters, storage registers
Block diagram view
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(*
(+
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(/
(0
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*
+
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0 !1
Selectively loaded – EN or LD input
Output enable – OE input
Multiple registers – group 4 or 8 in parallel
Point-to-point connection
dedicated wires
muxes on inputs of
each register
Common input from multiplexer
load enables
for each register
control signals
for multiplexer
Common bus with output enables
output enables and load
enables for each register
2
2
2
3,
2
2
3,
4
3,
3%
34
35
6%
64
65
-
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/
0
(-
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Collections of registers in one package
two-dimensional array of FFs
address used as index to a particular word
can have separate read and write addresses so can do both at same time
4 by 4 register file
16 D-FFs
organized as four words of four bits each
write-enable (load)
read-enable (output enable)
3
63
57
58
5)
5*
5+
5,
5-
5.
5.
5/
50
9$-
9$.
9$/
9$0
Larger collections of storage elements
implemented not as FFs but as much more efficient latches
high-density memories use 1 to 5 switches (transitors) per memory bit
Static RAM – 1024 words each 4 bits wide
once written, memory holds forever (not true for denser dynamic RAM)
address lines to select word (10 lines for 1024 words)
read enable
same as output enable
often called chip select
permits connection of many
chips into larger array
write enable (same as load enable)
bi-directional data lines
output when reading, input when writing
