Computer Organization: Language of the Computer - Lecture 8, Lecture notes of Computer Architecture and Organization

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CSE 311

Computer Organization

Mostafa I. Soliman

Professor of Computer Engineering

CSE Department

[email protected] [email protected]

Lecture 8

Instructions:

Language of the

Computer

Instructions: Language of the Computer

- HW Understands Machine Language ONLY - Instruction Set - Classifying Instruction Sets - Operand Locations - Operands in Instruction Sets - Addressing Modes - Operations in the Instruction Set - Encoding Instruction Set - Design Principles - Put All Together:

MIPS

All the great things are simple, and many can be expressed in a single word: freedom, justice, honor, duty, mercy, hope. Winston Churchill

Instruction Set

• To command a computer’s hardware, you must speak its language. - The words of a computer’s language are called instructions, and its vocabulary is called an instruction set.
• instruction set: The portion of the computer visible to the programmer or compiler writer

instruction set

Software

Hardware

Classifying Instruction Sets

• The type of internal storage in a processor is the most basic differentiation
• The major choices are
  • Stack
  • Accumulator
  • set of registers
• Operands may be named explicitly or implicitly.
• Stack architecture: Operands are implicitly on the top of the stack.
• Accumulator architecture: one operand is implicitly the accumulator.
• General-purpose register architectures have only explicit operands — either registers or memory locations.

Coding C = A + B

Why General-purpose Registers?

• faster than memory
• more efficient for compilers
• reusing loaded data

Operands in Instruction Sets

• Two/three Operands Instructions
  • In the three-operand format, the instruction contains one result operand and two source operands.
  • Example ADD R2, R3, R4 // R2  R3 + R
  • In the two-operand format, one of the operands is both a source and a result for the operation.
  • Example ADD AX, BX // AX  AX + BX
• How many of the operands may be memory

addresses

• The number of memory operands supported by a typical ALU instruction may vary from none to three.
• Type and Size of Operands
• Encoding in the opcode designates the type of an operand.
• character  8 bits, half word  16 bits, word  32 bits, single- precision (SP) floating point (FP)  32 bits, DP FP  64 bits

Addressing Modes

the left arrow (←) • is used for assignment the array Mem as • the name for main memory the array Regs for • registers. Mem[Regs[R 1 ]] refers to the contents of the memory location whose address is given by the contents of register 1 (R 1 ). d : The size of the data item being accessed

Operations in the Instruction Set

• The most widely executed instructions are the simple operations.
• 10 simple instructions account for 96% of instructions executed for a collection of integer programs running on the popular Intel 80x86.
• Categories of Instruction Operators

Encoding Instruction Set

• Three popular choices for encoding the instruction

set

• variable
• fixed
• hybrid

Design Principles

• Simplicity favors regularity. Regularity motivates many

features of the MIPS instruction set: keeping all

instructions a single size, always requiring three register

operands in arithmetic instructions, and keeping the

register fields in the same place in each instruction

format.

• Smaller is faster. The desire for speed is the reason that

MIPS has 32 registers rather than many more.

• Good design demands good compromises. One MIPS

example was the compromise between providing for

larger addresses and constants in instructions and

keeping all instructions the same length.

MIPS Assembly Language

Instruction Format

• op: Basic operation of the instruction, traditionally called

the opcode.

• rs: The first register source operand.
• rt: The second register source operand.
• rd: The register destination operand. It gets the result of

the operation.

• shamt: Shift amount. (the field contains zero if it is not

used)

• funct: Function. This field, often called the function code,

selects the specific variant of the operation in the op field.

MIPS Addressing Modes

MIPS Instruction Set

• Use general-purpose registers (32 registers)
• load-store architecture
• Support these addressing modes:
  • displacement (with an address offset size of 16 bits), » Register indirect » Direct (absolute)
  • immediate (16 bits), and
• Support these data sizes and types: 8, 16, 32, and 64 bits integers and 64 bits IEEE 754 floating-point numbers.
• Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and shift.
• Compare equal, compare not equal, compare less, branch (with a PC-relative address), jump, call, and return.
• Use fixed instruction encoding