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SAP-1 COMPUTER OVERVIEW
SAP-1 is the first stage in the evolution towards modern computers. The main purpose of SAP is to introduce all the crucial ideas behind computer operations. Being a simple computer, SAP-1 also covers many advanced concepts.
Main Features
- Simple-As-Possible
- One output device (8 LEDs)
- 16 bytes of read-only memory
- 5 instructions: 3 with 1 operand, 2 with implicit operands
- Accumulator architecture: Accumulator, Out Register, B Register, Memory Address Register (MAR) and Instruction Register (IR)
Architecture
- 8-bit "W" bus
- 4-bit program counter, only counts up (starts execution at 0)
- 4-bit Memory Address Register (MAR)
- 16x8-bit Memory
- 8-bit Instruction Register (IR)
- 6-cycle controller with 12-bit microinstruction word
- 8-bit Accumulator
- 8-bit B Register
- 8-bit Adder-Subtractor
- 8-bit Output Register
INTRODUCTION
SAP-1 is a bus organized computer. All registers are connected to the W bus with the help of tri-state buffers. A block diagram of SAP-1 is shown in figure below. A brief description of each box shown in the figure is as follows;
Program Counter Instructions to be executed are placed at the starting addresses of memory, e.g. the first instruction of a program will be placed at binary address 0000, the second instruction at address 0001, the third at address 0010, and so on. Now to execute one instruction, first step is to generate the address at which this instruction is placed in memory. So this address is generated by Program Counter, which can count from 0000 to 1111 (0 to 15). Because total memory locations are 16, Program Counter is a 4-bit counter.
Input and Memory Address Register (MAR) When SAP-1 is Running Mode , the address generated by the Program Counter is latched into the MAR through W bus. A bit later, the MAR applies this 4-bit address to the RAM, where a read operation is performed. When SAP-1 is in Programming Mode , the address generated with the help of switches is applied to the RAM.
The RAM The RAM is a 16 x 8 static TTL RAM. It means there are 16 memory locations (from 0 to 15) and each location contains an 8-bit of data/instruction. You can program the RAM by means of the switches to be used for address and data. This allows you to store a program and data in the memory before a computer run. During a computer run, the RAM receives 4-bit addresses from the MAR and a read operation is performed, in this way, the instruction or data stored in the RAM is placed on the W bus for use in some other part of the computer.
Instruction Register (IR) The Instruction Register is part of the Control Unit. To fetch an instruction from the memory the computer does a memory read operation. This places the contents of the addressed memory location on the W bus. At the same time, the Instruction Register is set up for loading on the next positive clock edge. The contents of the instruction register are split into two nibbles. The upper nibble is a two-state output that goes directly to the block labeled "Controller-sequencer" The lower nibble is a three- state output that is read onto the W bus when needed.
Controller Sequencer The 12 bits coming out of the Controller Sequencer form a word that controls the rest of the computer. Before each operation a Clear (CLR) signal resets the computer. The 12 wires carrying the control word are called the Control Bus. The control word has the format:
CON = C P EP LM CE L 1 E 1 LA EA SU EU LB LO
This word determines how the registers will react to the next positive clock (CLK) edge. For instance a
high E P and a low LM means that the contents of Program Counter are latched into MAR on the next
positive clock edge. As another example, a low CE and a low L A mean that the addressed RAM word
will be transferred to the accumulator on the next positive clock edge.
Accumulator The accumulator register is a buffer register that stores intermediate values in a computer operation. The block diagram shows Accumulator has two outputs. One output goes t the adder/subtractor and other goes to the bus.
Adder-Subtractor
SAP-1 uses a 2's complement adder-subtractor. When SU is low, the sum is:
S = A + B
When SU is high, the sum is:
S = A + B'
The Adder-subtractor is asynchronous and its contents change as soon as the input changes.
B Register This is another buffer register. It is used in arithmetic operations. It supplies the number to be added or subtracted from the contents of accumulator to the adder-subtractor.
Output Register At the end of an arithmetic operation the accumulator contains the word representing the answer; it is then loaded into the output register to be displayed to the outside world through the Binary Display.
Binary Display The binary display is a row of 8 LEDs. Since each LED is connected to one flip-flop of the output port, the binary display shows the contents of the Output register.
