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3&4-MAKING INSTRUCTION DECODER, RING COUNTER & CONTROL
MATRIX
The purpose of these labs is to build the circuit of the Control Unit of SAP-1 computer which includes Instruction Decoder, Ring Counter and the Control Matrix. Together these components generate the 12-bit Control Word for SAP-1.
Components Required
- Quad Two-Input NAND Gate, 74LS00-----------------(6)
- Tri Three-Input NAND Gate, 74LS10------------------(1)
- Dual Four-Input NAND Gate, 74LS20-----------------(5)
- Hex Inverter, 74LS04----------------------------------(5)
- Dual J-K Flip Flop, 74LS107----------------------------(3)
- Connecting Wires
SAP-1 Instruction Set SAP-1 computer has a set of five instructions. This instruction set is a list of basic operations this computer can perform. The instructions are:
Mnemonics
LDA, ADD, SUB, OUT and HLT represent the abbreviated form of the instruction set called Mnemonics.
Memory-Referenced Instructions LDA, ADD and SUB are memory-referenced instructions because they use the data stored in memory. OUT and HLT are not memory-referenced instructions since they do not use the data stored in memory.
LDA LDA stands for "Load the Accumulator". A complete LDA instruction includes the hexadecimal address of the data to be loaded. For instance, LDA 8H means load the accumulator with the data 8H.
ADD
ADD is another SAP-1 instruction. A complete ADD instruction includes the address of the word to be added. For instance Add 9H means add the contents of memory location 9H to the contents of the accumulator; the sum replaces the original contents of accumulator. First the contents of 9H are loaded into B register, and instantly the adder-subtractor forms the sum of A and B.
SUB A complete SUB instruction includes the address of the word to be subtracted. For example SUB CH means subtract the contents of memory location CH from the contents of the accumulator. First, contents of CH are loaded into B register and then instantly the adder-subtractor forms the difference of A and B.
OUT The OUT instruction transfers the contents of accumulator to the Output port. After the execution, the answer to the problem in the program can be seen on the LED display. OUT is not memory-referenced instruction; it does not need an address.
HLT HLT stands for Halt. This instruction tells the computer to stop processing the data. HLT marks the end of a program similar to the way a period marks the end of a sentence. You must use a HLT instruction at the end of every SAP-1 program, otherwise you get computer trash. HLT is complete in itself; it does not require RAM word since this instruction does not involve memory.
Programming SAP- To load an instruction in memory we use some kind of code that the computer can interpret. Following table shows a set of codes. The number 0000 is a code for LDA, 0001 for ADD, 0010 for SUB, 1110 for OUT and 1111 for HLT. Since a code tells the computer which operation to perform, it is called Opcode.
Mnemonic Opcode
LDA 0000
ADD 0001
SUB 0010
OUT 1110
HLT 1111
Address State The T1 state is called the address state because the address in the PC is transferred to the MAR during this state. During this state, Ep and Lm are active; all other control bits are inactive. This means that the controller sequencer is sending out a control word of:
CON = CpEpLmCE L1E1LaEa SuEuLbLo 0 1 0 1 1 1 1 0 0 0 1 1
Increment State During the Increment State T2, only Cp is active, causing the PC to increment to the next memory location.
CON = CpEpLmCE L1E1LaEa SuEuLbLo 1 0 1 1 1 1 1 0 0 0 1 1
Memory State The T3 state is called the memory state because the addressed RAM instruction is transferred from the memory to the Instruction Register. The only active control bits are CE and L1 and the word out of the controller is:
CON = CpEpLmCE L1E1LaEa SuEuLbLo 0 0 1 0 0 1 1 0 0 0 1 1
Fetch Cycle The address, increment and memory states are called the fetch cycle of SAP-1.
Execution Cycle The next three states T4 T5 T6 are three states of the execution cycle of SAP-1. The register transfer during this execution depends on a particular instruction being executed. Each instruction has its own control routine.
Fig-
Control Matrix
Fig-4 Instruction Decoder, Ring Counter & Control Matrix
