Edgetriggering
In edge triggering the circuit
becomes active at negative or
positive edge of the clock signal.
Pulse triggering
pulse-triggered means that data
are entered into the flip-flop on
the rising edge of the clock
pulse, but the output does not
reflect the input state until the
falling edge of the clock pulse
SR latch
An SR latch (Set/Reset) is an
asynchronous device: it works
independently of control signals
and relies only on the state of
the S and R inputs. In the image
we can see that an SR latch can
be created with two NOR gates
that have a cross-feedback loop
SR Flip Flop
An SR Flip Flop (also referred to
as an SR Latch) is the most
simple type of flip flop. It has
two inputs S and R and two
outputs Q and Q’ . The state of
this latch is determined by the
condition of Q. If Q is 1 the latch
is said to be SET and if Q is 0 the
latch is said to be RESET. This SR
Latch or Flip flop can be
designed either by two cross-
coupled NAND gates or two-
cross coupled NOR gates. When
we design this latch by using
NOR gates, it will be an active
high S-R latch. That means it is
SET when S = 1. When we
design this latch by using NAND
gates, it will be an active low S-
R latch. That means it is SET
when S = 0. SR Flip Flop is also
called SET RESET Flip Flop
JK flip flop
The JK flip flop is a universal flip
flop having two inputs 'J' and
'K'. In SR flip flop, the 'S' and 'R'
are the shortened abbreviated
letters for Set and Reset, but J
and K are not. The J and K are
themselves autonomous letters
which are chosen to distinguish
the flip flop design from other
types.
Master Slave JK flip flop
The Master-Slave Flip-Flop is
basically a combination of two
JK flip-flops connected together
in a series configuration. Out of
these, one acts as the “master”
and the other as a “slave”. The
output from the master flip flop
is connected to the two inputs
of the slave flip flop whose
output is fed back to inputs of
the master flip flop. In addition
to these two flip-flops, the
circuit also includes an inverter.
The inverter is connected to
clock pulse in such a way that
the inverted clock pulse is given
to the slave flip-flop. In other
words if CP=0 for a master flip-
flop, then CP=1 for a slave flip-
flop and if CP=1 for master flip
flop then it becomes 0 for slave
flip flop.
Working of a master slave flip
flop – 1. When the clock pulse
goes to 1, the slave is isolated; J
and K inputs may affect the
state of the system. The slave
flip-flop is isolated until the CP
goes to 0. When the CP goes
back to 0, information is passed
from the master flip-flop to the
slave and output is obtained. 2.
Firstly the master flip flop is
positive level triggered and the
slave flip flop is negative level
triggered, so the master
responds before the slave. 3. If
J=0 and K=1, the high Q’ output
of the master goes to the K
input of the slave and the clock
forces the slave to reset, thus
the slave copies the master. 4. If
J=1 and K=0, the high Q output
of the master goes to the J
input of the slave and the
Negative transition of the clock
sets the slave, copying the
master. 5. If J=1 and K=1, it
toggles on the positive
transition of the clock and thus
the slave toggles on the
negative transition of the clock.
6. If J=0 and K=0, the flip flop is
disabled and Q remains
unchanged.
Timing Diagram of a Master flip
flop
When the Clock pulse is high
the output of master is high and
remains high till the clock is low
because the state is stored,
Now the output of master
becomes low when the clock
pulse becomes high again and
remains low until the clock
becomes high again
D flip-flop
The D (data) flip-flop is a slight
modification of the S R flip-flop
• An S R flip-flop is converted to
a D flip-flop by inserting an
inverter between S and R and
assigning the symbol D to the
single input • sampled during
the occurance of a clock
transition from 0 to 1 • if D=1,
the output of the flip-flop goes
to the 1 state, but if D=0,the
output of the flip-flop goes to
the 0 state
T flip-flop /Toggle flip-flop •
T flip-flop is the simplified
version of JK flip-flop. • Here
from a JK flip-flop when input J
and K are connected to provide
a single designated by T. ie, it is
obtained by connecting the
same input 'T' to both input of
JK flip-flop • The T flip-flop
there for has only 2 condition .
When T+0(j=k=0) a clock
transition does not change the
state of the flip-flop. • When
T=1 (J=K=1) a clock transition
complements the state of the
flip-flop. • The condition can be
expressed by a characteristic
equation. Q (t+1) =Q(t) (+) T
Shift Registers
• Flip flops can be used to store
a single bit of binary data (1or
0). However, in order to store
multiple bits of data, we need
multiple flip flops. • N flip flops
are to be connected in an order
to store n bits of data. 20 • A
Register is a device which is
used to store such information.
It is a group of flip flops
connected in series used to
store multiple bits of data. • The
information stored within these
registers can be transferred
with the help of shift registers.
• Shift Register is a group of flip
flops used to store multiple bits
of data.
