VHDL: Understanding Concurrent Signal Assignments and Decoders, Slides of Digital Logic Design and Programming

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Lecture

• Agenda
  1. VHDL : Concurrent Signal Assignments
  2. Decoders using Structural VHDL
• Announcements
  1. HW #4 due
  2. HW #5 assigned

Sequential Logic Design

Concurrent Signal Assignments

• Concurrency
  • the way that our designs are simulated is important in modeling real HW behavior
  • components are executed concurrently (i.e., at the same time)
  • VHDL gives us another method to describe concurrent logic behavior called

"Concurrent Signal Assignments"

• we simply list our signal assignments (<=) after the "begin" statement in the architecture
• each time any signal on the Right Hand Side (RHS) of the expression changes, the Left Hand Side (LHS) of the assignment is updated.
• operators can be included (and, or, +, …)

Concurrent Signal Assignments

• Concurrent Signal Assignment Example

node1 <= A xor B; X <= node1 or C;

• if these are executed concurrently, does it model the real behavior of this circuit?

Yes, that is how these gates operate. We can see that there may be timing that needs to be considered….

• When does C get to the OR gate relative to (A ⊕ B)?
• Could this cause a glitch on X? What about a delay in the actual value?

node

Conditional Signal Assignments

• Conditional Signal Assignments
  • we can also include conditional situations in a concurrent assignment
  • the keywords for these are:

"when" = if the condition is TRUE, make this assignment "else" = if the condition is FALSE, make this assignment

ex) X <= '1' when A='0' else '0'; Y <= '0' when A='0' and C='0' else '1';

• X and Y are evaluated concurrently !!!
• notice that we are assigning static values (0 and 1), this is essentially a "Truth Table"
• if using this notation, make sure to include every possible input condition, or else you haven't described the full operation of the circuit.

Selected Signal Assignments

• Selected Signal Assignment
  • We can also use a technique that allows the listing of "choices" and "assignments" in a comma delimited fashion.
  • this is called "Selected Signal Assignment" but it is still CONCURRENTLY assigned

syntax:

with expression select

signal-name <= signal-value when choices, signal-value when choices, : signal-value when others;

• we use the term "others" to describe any input condition that isn't explicitly described.
• Note the difference between , and ;

Selected Signal Assignments

• Selected Signal Assignment Example

Describe the following Truth Table using Selected Signal Assignments:

Input X 000 0 001 1 010 1 011 0 100 1 101 1 110 0 111 0 begin with Input select X<= '0' when "000", '1' when "001", '1' when "010", '0' when "011", '1' when "100", '1' when "101", '0' when "110", '0' when "111";

Decoders using Structural VHDL

• Decoders
  • a decoder has n inputs and 2 n^ outputs
  • one and only one output is asserted for a given input combination

ex) truth table of decoder

Input Output 00 0001 01 0010 10 0100 11 1000

• these are key circuits for a Address Decoders

Decoders using Structural VHDL

• Decoder Structure
  • The output stage of a decoder can be constructed using AND gates
  • Inverters are needed to give the appropriate code to each AND gate
  • Using AND/INV structure, we need:

2 n^ AND gates n Inverters

Showing more inverters than necessary to illustrate concept