VHDL Programming: Concurrent Statements and Logic Design in Chapter 3, Slides of Computer Science

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STRUCTURED LOGIC DESIGN WITH

VHDL – part 2

Reference:

“Structured Logic Design With VHDL”

James R. Armstrong, F. Gail Gray

Virginia Tech

Concurrent Statements

• They are used

within architectures

• NOT executed in the order

written;

only when signal that affect

the value computed by the

statement changes

• Plus, executed once

at the beginning of

simulation

Process Statement (1)

• Fundamental statement

type

• All other concurrent

statements can be written as

processes

• Label and sensitivity list are

optional

• Executed once at the

beginning of simulation and

when any signal in sensitivity

list changes

LABEL: process (sensitivity_signal_list) {constant_declarations} {var_declarations} begin {sequential_statements} end process LABEL;

Assert Statement (concurrent)

• If BOOL_EXPR is false

then Message_string

is written to the

output device

LABEL: assert BOOL_EXPR report “Message_string” severity SEVERITY_LEVEL;

LABEL: assert (A or B)=C report “C is NOT equal A or B” severity WARNING;

LABEL: process (A, B, C) begin assert (A or B) = C report ”...” severity WARNING; end process LABEL;

Upper two examples are

equivalent

Concurrent Signal Assignment

Statement (1)

• Executed:
  • once at the beginning of

the simulation

• at any time any

right side signal

experiences an event

• Example: following code will

execute

when A or B changes

LABEL: C <= A or B;

• This simple example is

equivalent to the

following process:

LABEL: process (A, B) begin C <= A or B; end process LABEL;

Functions (1)

• Declared by specifying:

– the name of the function

– the input parameters (if any)

– the type of the returned value

– any declarations required by the function itself

– an algorithm for the computation of the

returned value

Functions (2)

Procedures (2)

Subprogram Usage Rules (1)

• For procedures:

– parameters modes: in, out, inout

– parameters object classes:

constant, variable, signal

– if the mode is in and no object class is specified,

constant is assumed

– if the mode is inout or out and if

no object class is specified,

variable is assumed

Main Topics in Chapter 3

Concurrent Statements

Packages & Libraries

Input/Output Files

Packages (1)

• Use them to hold frequently used

declarations

• VHDL defines a STANDARD package

• Visible by referring to the package name

• Don’t forget to declare the package first

• Example:

package HANDY is subtype BITVECT3 is BIT_VECTOR(0 to 2); function MAJ3 (X: BIT) return BIT; end HANDY;

Visibility (1)

• Region is a logical continuous portion of text

• Declaration region is a region in which a name

can be used to unambiguously refer to a

declared entity

• The word entity is used in its general sense,

not the specialized meaning of a design entity

Visibility (2)

• Once an entity has been declared in the

declaration region, its name is visible to the

end of the declaration region

• Two types of visibility:

– directly, within the region where entity is declared

– by selection, through use and library clauses