Contact Bounce - Digital Systems - Exam, Exams of Digital Systems Design

Main points of this past exam are: Contact Bounce, Truth Table, Distributive Law, Boolean Algebra, Expressions, Boolean Logic Expression, Karnaugh Map

Typology: Exams

2012/2013

Uploaded on 03/30/2013

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Cork Institute of Technology
Higher Certificate in Engineering in Electronic Engineering - Stage 1
(National Certificate in Engineering in Electronic Engineering – Stage 1)
(NFQ - Level 6)
Summer 2005
Digital Systems
(Time: 3 Hours)
Answer any five questions [20 marks each]
Maximum available marks is 100.
Examiners: Mr. J.J. O’Sullivan
Mr. J. Berry
Dr. R. O’Dúbhghaill
Q1 (a) Use a truth table to prove the Distributive Law of Boolean algebra below
A
(
B
+C)
=
A
B
+
A
C [4 marks]
(b) Using Boolean algebra only, minimise the following expressions
i)
X=ACB
+
BAC
+
C A B
ii)
Y=AB(A+C)+B(A+AB) [8 marks]
(c) Convert the following Boolean logic expression into standard sum-of-products
form.
Z=ABCD+ABCD
+
ABC
+
A BCD
+
ACD
+
ABCD [2 marks]
(d) Minimise the sum-of-products expression in (c) using a Karnaugh map. [6 marks]
Q2 In an automated bottling plant, a valve will open to fill each bottle when the bottle
moves into position, and the valve will close once the liquid in the bottle reaches the
full level. The plant is controlled by a logic circuit which has the following inputs
from sensors:- valve open (V), bottle in position (P), bottle full (F).
The output (Z) from the logic circuit will sound an alarm and stop the plant if the valve
opens before a bottle moves into position, or if the valve fails to close when a bottle is full.
For the logic circuit specified above,
(a) derive a complete truth table for the output (Z) [4 marks]
(b) from the truth table, obtain a sum-of-products expression [2 marks]
(c) using Boolean algebra or a K-map, minimise the expression [4 marks]
(d) for the minimised expression, draw a basic logic circuit [4 marks]
(e) convert this circuit to one using NAND gates only [6 marks]
pf3
pf4

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Cork Institute of Technology

Higher Certificate in Engineering in Electronic Engineering - Stage 1

(National Certificate in Engineering in Electronic Engineering – Stage 1)

(NFQ - Level 6)

Summer 2005

Digital Systems

(Time: 3 Hours)

Answer any five questions [20 marks each] Maximum available marks is 100.

Examiners: Mr. J.J. O’Sullivan Mr. J. Berry Dr. R. O’Dúbhghaill

Q1 (a) Use a truth table to prove the Distributive Law of Boolean algebra below A ( B + C ) = AB + AC [4 marks]

(b) Using Boolean algebra only, minimise the following expressions i) X = ACB + B AC + C A B ii) Y = AB ( A + C ) + B ( A + AB ) [8 marks] (c) Convert the following Boolean logic expression into standard sum-of-products form. Z = ABCD + ABCD + ABC + A BCD + ACD + ABC D [2 marks] (d) Minimise the sum-of-products expression in (c) using a Karnaugh map. [6 marks]

Q2 In an automated bottling plant, a valve will open to fill each bottle when the bottle

moves into position, and the valve will close once the liquid in the bottle reaches the full level. The plant is controlled by a logic circuit which has the following inputs from sensors:- valve open ( V ), bottle in position ( P ), bottle full ( F ).

The output ( Z ) from the logic circuit will sound an alarm and stop the plant if the valve opens before a bottle moves into position, or if the valve fails to close when a bottle is full.

For the logic circuit specified above, (a) derive a complete truth table for the output ( Z ) [4 marks] (b) from the truth table, obtain a sum-of-products expression [2 marks] (c) using Boolean algebra or a K-map, minimise the expression [4 marks] (d) for the minimised expression, draw a basic logic circuit [4 marks] (e) convert this circuit to one using NAND gates only [6 marks]

Q3 (a) With the aid of a timing diagram, explain what is meant by contact bounce. [4 marks]

(b) Figure 1 below shows the circuit of a simple de-bounce circuit similar to that studied in the FACET system. Analyse the circuit carefully, and describe in detail what happens when the switch, Sw , changes to the lower position. [6 marks] (c) Draw a logic symbol and truth table for a positive edge triggered J-K flip-flop complete with active-LOW asynchronous preset and clear inputs. [4 marks] (d) Complete the timing diagram, Figure 4 on the return sheet for this circuit. [6 marks]

O/P

+5V

0V

Sw

Figure 1

Q4 (a) Explain briefly the difference between a half-adder and a full-adder. [2 marks]

(b) Draw a block diagram of a full-adder and using the laws of binary addition, construct a truth table for this circuit. [4 marks] (c) Using the circuit in (b), draw a detailed logic diagram of a circuit capable of adding any two 4-bit binary numbers. [6 marks] (d) Figure 2 below is a pinout diagram of a 74LS283 4-bit adder chip. Draw a functional block diagram to show how a number of these chips would be wired up to implement a practical 8-bit adder circuit. [8 marks]

7 8

10 9

Gnd

1 2 3 4 5 6

Vcc 16 15 14 13 12 11

A2 Σ 1 A1 B

B3 A3 Σ 3 A C

Σ 4

B2 C

B Σ 2

Figure 2