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5 problems, 4 pages Final Exam Solutions 2 May 2001
Problem 1 (3 parts, 30 points) Counters
Part A (10 points) Design a toggle cell using transparent latches, 2-input XOR gates, and 2-input basic gates (AND, OR, NAND, NOR, and NOT). Include a toggle enable TE, active low clear CLR, and a two-phase non-overlapping clock PHI1 and PHI2. Label the output OUT.
In Out
En
Latch
In Out
En
Latch
TE Out
CLR
Part B (10 points) Now use copies your toggle cells (in icon form) to build a divide by eight counter. This design should include an active high external count enable CE and an active high external clear CLR. You do not need to draw in the clock signals. Assume all toggle cells are connected to the two-phase clock. Label all of your output signals.
TE Out Clr
TE Out Clr
TE Out Clr
O 0
O 1
O 2
Ext Clr
Ext CE
5 problems, 4 pages Final Exam Solutions 2 May 2001
Part C (10 points) Now use copies of your toggle cell (in icon form) to build a divide by three counter. This design should include an active high external count enable CE and an active high external clear CLR. Your design should clear if (A) the external clear CLR is high, or (B) the maximum output count is reached and the count enable is high. You do not need to draw in the clock signals.
O 0
O 1
Ext Clr
Ext CE TE Out Clr
TE Out Clr
Problem 2 (3 part, 30 points) Storage
Part A (10 points) Implement a transparent latch using only pass gates and inverters. Label all inputs and outputs.
In Out
En
Part B (10 points) Draw the circuit for a six transistor static RAM cell. Label all signals. D D
S
Part C (10 points) The IBM PC XT used 64K address by 1 bit word DRAM chips. How many of these chips would be needed to create a 16M address by 64 bit word memory system used in today’s PCs (show work)?
chips needed = 16M address x 64 bit/word / 64K bit = 2^24 x 2^6 / 2 16 = 2 14 = 16K chips
5 problems, 4 pages Final Exam Solutions 2 May 2001
Problem 4 (4 parts, 20 points) Arithmetic
For each problem below, (a) compute the operations using the rules of subtraction, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
0 1 0 0
subtraction result 1 0 0 1 0 1 1 1 0 1 0 1 1 0 0 1 signed error? yes yes no no unsigned error? yes no yes yes
Problem 5 (2 parts, 20 points) Gate and Switch Design
Part A (10 points) Implement the following function using only 2 and 3 input NAND gates and inverters. Use mixed logic notation. Only the uncomplemented signals are available. Do not simplify.
Out = ( A + B )+ C ⋅ D ⋅ E
A
B
C
D
E
Out
Part B (10 points) Implement the following function using N and P type switches and wire. Assume both signals and their complements are available.
Out =( A + B + C )⋅ D ⋅( E + F )
A
B
C
D
E
F
A B C
D
E F Out
