Counters One - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda
  1. Counters
• Announcements
  1. HW #13 assigned
  2. Next: Test #2 Review

• Counters in VHDL
  • strong type casting in VHDL can make modeling counters difficult (at first glance)
  • the reason for this is that the STANDARD and STD_LOGIC Packages do not define "+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types

• Counters in VHDL using STD_LOGIC_UNSIGNED

use IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

• Counters in VHDL using STD_LOGIC_UNSIGNED architecture counter_arch of counter is signal count_temp : std_logic_vector(3 downto 0); -- Notice internal signal begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= "0000"; elsif (Clock='1' and Clock'event) then if (Direction='0') then count_temp <= count_temp + '1'; -- count_temp can be used on both LHS and RHS else count_temp <= count_temp - '1'; end if; end if; end process; Count_Out <= count_temp; -- assign to Port after the process end counter_arch;

• Counters in VHDL using STD_LOGIC_ARITH

use IEEE.STD_LOGIC_ARITH.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

• Counters in VHDL using STD_LOGIC_ARITH architecture counter_arch of counter is signal count_temp : integer range 0 to 15; -- Notice internal integer specified with Range begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= 0; -- integer assignment doesn't requires quotes elsif (Clock='1' and Clock'event) then if (count_temp = 15) then count_temp <= 0; -- we manually check for overflow else count_temp <= count_temp + 1; end if; end if; end process; Count_Out <= conv_std_logic_vector (count_temp, 4); -- convert integer into a 4-bit STD_LOGIC_VECTOR end counter_arch;

• Ring Counters in VHDL
  • to mimic the shift register behavior, we need access to the signal value before and after clock'event
  • consider the following concurrent signal assignments: architecture …. begin Q0 <= Q3; Q1 <= Q0; Q2 <= Q1; Q3 <= Q2; end architecture…
  • since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire

• Ring Counters in VHDL
  • since a process doesn't assign the signal values until it suspends, we can use this to model the "before and after" behavior of a clock event. process (Clock, Reset) begin if (Reset = '0') then Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process
  • notice that the signals DO NOT appear in the sensitivity list. If they did the process would continually execute and not be synthesized as a flip-flop structure

• Linear Feedback Shift Register Counters in VHDL

process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3 xor Q2; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process

• Multiple Processes
  • we can now use State Machines to control the start/stop/load/reset of counters
  • each are independent processes that interact with each other through signals
  • a common task for a state machine is:
    1. at a certain state, load and enable a counter
    2. go to a state and wait until the counter reaches a certain value
    3. when it reaches the certain value, disable the counter and continue to the next state
  • since the counter runs off of a clock, we know how long it will count between the start and stop