CPU Structure-Microprocessor and Computer Architecture-Lecture Slides, Slides of Computer Architecture and Organization

This lecture was delivered by Prof. Sai Tiwari at B R Ambedkar National Institute of Technology. This lecture is part of lecture series on Microprocessor and Computer Architecture course. It includes: Normal, Abnormal, Sexual, Fetal, Embrionic, Urogenital, Androgen, Syndromes, Reseptor, Genitalia

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2011/2012

Uploaded on 07/26/2012

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CPU Structure
zCPU must:
zFetch instructions
zInterpret instructions
zFetch data
zProcess data
zWrite data
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CPU Structure z

CPU must: z Fetch instructions z Interpret instructions z Fetch data z Process data z Write data

CPU With Systems Bus

Registers z

CPU must have some working space(temporary storage) z Called registers z Number and function vary betweenprocessor designs z One of the major design decisions z Top level of memory hierarchy

User Visible Registers z

General Purpose z Data z Address z Condition Codes

General Purpose Registers (Cont) z

Make them general purpose z Increase flexibility and programmer options z Increase instruction size & complexity z Make them specialized z Smaller (faster) instructions z Less flexibility

How Many GP Registers? z

Between 8 - 32 z Fewer = more memory references z More does not reduce memory referencesand takes up processor real estate

Condition Code Registers z

Sets of individual bits z e.g. result of last operation was zero z Can be read (implicitly) by programs z e.g. Jump if zero z Can not (usually) be set by programs

Control & Status Registers z

Program Counter z Instruction Decoding Register z Memory Address Register z Memory Buffer Register

Supervisor Mode z

Kernel mode z Allows privileged instructions to execute z Used by operating system z Not available to user programs

Other Registers z

May have registers pointing to: z System Stack pointer z Interrupt Vectors z CPU design and operating system designare closely linked

SUMMARY