Intel Core 2 Duo Processor: Architecture, Microarchitecture, Models, and Features, Slides of Computer Architecture and Organization

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Intel Core 2 Duo

Desktop Processor Architecture

What’s next?

• History
• Intel Core 2 Duo
• Intel Core 2 Microarchitecture
• Intel Core 2 Models
• Architectural Features of Core 2
• What is an instruction set?
• SSSE3 (x86)
• Execute Disable Bit
• Intel ®^ Wide Dynamic Execution
• 14 Stage pipeline
• MacroFusion
• Micro-op Fusion
• What is L1 and L2?
• Intel ®^ Advanced Smart Cache
• Intel ®^ Smart Memory Access
• Intel ®^ Advanced Digital Media Boost

Intel Core 2 Duo

Intel Core 2 Microarchitecture

Merom

Conroe

Woodcrest

65nm

Server

Optimized

Desktop

Optimized

Mobile

Optimized

Intel®^ Wide Dynamic Execution

Intel® Intelligent Power Capability

Intel® Advanced Smart Cache

Intel®^ Smart Memory Access

Intel® Advanced Digital Media Boost

Intel Core 2 models

• Woodcrest - 65 nm process technology
  • Server optimized CPU
  • Introduced on July 26, 2006
  • Same features as Conroe
  • Variants
    • Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
    • Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
    • Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
    • Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
    • Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
    • Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
    • Xeon 5148LV - 2.33 GHz (4 MB L2,1333 MHz FSB,40 W)

Intel Core 2 models

• Merom - 65 nm process technology
  • Mobile CPU
  • Introduced on July 27, 2006
  • Same features as Conroe
  • Variants
    • Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
    • Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
    • Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
    • Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
    • Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB)
    • Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB)

What is an instruction set?

• All instructions, and all their variations, that a processor can execute
• Types:
  • Arithmetic such as add and subtract
  • Logic instructions such as and, or, and not
  • Data instructions such as move, input, output, load, and store
• Part of the computer architecture
• Distinguished from the microarchitecture
• Different microarchitectures can share common instruction set while their

internal designs differ

Fetch Decode

Operand

Fetch

Execute Retire

SSSE3 (x86)

Supplemental Streaming SIMD Extension 3

• Intel's name for the SSE instruction set's fourth iteration
• Single Instruction Multiple Data instruction set
• A revision of SSE
• CPUs with SSSE
  • Xeon 5100 series
  • Intel Core 2
• Development
  • Faster permutation of bytes
  • Multiplying 16-bit fixed-point numbers with correct rounding
  • Better word accumulation

Execute Disable Bit

• Problem

• Buffer overflow attacks of malicious software

• Must be combined with a supporting operating system

• Classifies areas in memory for protection

• Disables code execution on an attack

• Decreases the need for software patches and antivirus

software

Intel

Wide Dynamic Execution

• Advantage

Wider execution

Comprehensive Advancements

Enabled in each core

Each core fetches, dispatches, executes and returns up to four full instructions simultaneously.

Performance increases while energy consumption decreases

Branch – Add – Mul – Load - Store

L 2 C A C H E

14 Stage pipeline

• Pentium D has 31 stage pipeline

• AMD Athlon 64 has 12 stage pipeline

• A question for the class:

– Why didn’t Intel increase the pipeline after a 31 stage

experience with Pentium D?

I100 I

I3 I2 I

Jump!

Bubble of non-work

MacroFusion

• If (myVariable == myConstant)

doThis();

Else

doThat();

Compare instruction

Jump instructions

Compare + Jump = microOp

What is L1 and L2?

• Level-1 and Level-2 caches

• The cache memories in a computer

• Much faster than RAM

• L1 is built on the microprocessor chi itself.

• L2 is a seperate chip

• L2 cache is much larger than L1 cache

Intel

Advanced Smart Cache

Decreased traffic

Increased traffic

Higher cache hit rate Reduced bus traffic Lower latency to data

• Advantage

L2 cache is shared equally

Data stored in one place

Optimizes cache resource

Up to 100% utilization of L2 cache