Digital Circuit Testing: Combinational Circuits, Fault Detection, EX-OR Method, Fault Tabl, Slides of Digital Systems Design

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Digital Circuit Testing

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Testing of Combinational Circuit

• Complex submicron chips / multi-chip PCBs  possibility of errors in the manufacturing process  physical faults in the digital circuits
• Need to test at manufacturer before shipping out
• Need to test periodically at user end as faults can also develop due to various circuit stresses (high temp, moisture, impact, etc.)
• Testing Scenarios
  • Fault-detecting test set (FDTS): inputs (test vectors) detecting presence/absence of faults (under certain assumptions, e.g., single fault).
  • Fault-locating test set (FLTS): inputs locating the fault(s).
  • CUT: Circuit under test.
  • Signature: Compaction of all O/Ps
• Fault Models
  • Types: permanent, intermittent, transient responses
  • Many possible physical faults: E.g., broken or shorted wires, defective transistors, noise, improper power voltage

Wire break (s-a-0) Wire short to GND (s-a-0) (^) Defective transistor (always on)

s-a-on s-a-

V (^) dd

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Function Notations in Fault Circuits

f(x 3 )=x 1 x 2 +x 3

For f(x n )=f(x 1 , x 2 ,…,x n ), let p be a wire in the circuit and d in

{0,1}. Then f p/d (x 1 ,…,x n ) is the function for the faulty circuit with wire p s-a-d. E.g., f 3/0 ( )=x 1 x 2 , and f 2/1 ( )=x 1 +x 3 1 x 1 x 2 x 3

2^ f3/ 3

4 5 s-a-

1 x 1 x 2 x 3

2 3

4 (^5) f

1 x 1 x 2 x 3

2 3

4 s-a-0^5 f2/

x 3 x 3

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…

Fault Testing

• Circuits with r wires have 2r different single faults and 3 r -1 possible single/multiple faults.
• Exhaustive testing is impractical for large circuits since it take O(2 n ) time for n-inputs.

Tests Response

x 1 x 2 x 3 Ckt o/p

Exp. resp 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1

CUT Test vector

… O/Ps

Expected responses

Compare

• Need to determine a minimum set of inputs that can test for (detect/catch) any single fault. Single fault detection is a good goal as:
  • Probability of multiple faults is much lower than single faults
  • Mutiple faults take much more time to detect Docsity.com

EX-OR Method

• MTs of F p/d =f + f p/d^ are tests for p/d. Can be determined algebraically
• E.g., In the previous example, F 1/0 =(x 1 x 2 +x 3 ) + x 3 =x 1 x 2 x 3. Hence, test=110 (only MT for F 1/0^ ) for 1/ F 3/0 =(x 1 x 2 +x 3 ) + x 1 x 2 = x 1 x 3 +x 2 x 3. Hence, test=001, 011,101 (MTs of F 3/0 )
• These tests (MTs of F p/d) can also be determined in a tabular manner as shown below, but this is more cumbersome

Tests Functions realized by Faulty Circuits x 1 x 2 x 3 f f 1/0^ f 2/1^ f 3/0^ f + f 1/

f + f 2/

f + f 3/

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 Docsity.com

Fault Table

• Displays a set of faults (generally single faults) and a set of test inputs that test them (i.e., detect them)
• A “1” at the intersection of i/p vector X nj^ and fault p/d  X nj^ is a test for p/d
• A “0” at the intersection of i/p vector X nj^ and fault p/d  X nj^ is not a test for p/d

Tests Faults x 1 x 2 x 3 1/0 1/1 2/0 2/1 3/0 3/1 4/0 4/1 5/0 5/ 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0

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Path Sensitizing method

• Path Sensitizing method
  • 1. Select a path from fault-site p to ckt. o/p(s). For fault p/d, z is the “fault value” ( z = d if there is a fault p/d)
  • 2. Forward Trace (FT) :
    • Choose intermediate logic values at gate i/ps along the path, so that logic values of lines/wires in the path are functions of z (i.e., z or z’).
    • Also, choose the complement value d’ to the fault value to be “injected” at the fault line ( for no fault @ p, z = d’ )
    • The path is then said to be “sensitized” from the fault site to the o/p.
  • 3. Backward Trace (BT) :
    • Trace backwards and establish circuit inputs, if possible, required for obtaining the logic values at different points in the sensitized paths determined during FT.
    • If there is a “conflicting” values needed at any i/p or intermediate points/wires during BT  thre is no test for p/z
    • Don’t cares (X’s) at i/ps after BT w/ no conflict anywhere else  multiple tests for p/z (<= 2k tests if k i/ps have X’s after BT)
  • This method may not yield all possible tests for a fault p/d (unlike the XOR method) - This can compromise minimal test set determination - If the reqd values shown above for wires p, p 1 , p 2 and p 3 , can be “injected” into them via some TV at the ckt i/ps (such TV(s) are determined during BT)  we have a test for p/d, since: - If there is a fault p/d, z = d , and o/p = z’ = d’ - If there is no fault @ p, z = d’ ( d’ is injected at p)  o/p = z’ = d - Thus o/p for p/d != o/p for no fault @ p

s-a-d (p/d)

z

d’

0

1

0

z

z

Wire p

p 1

p 2

p 3 I/P cone of p 3

Circuit I/Ps

BT

BT BT

BT

z’ s-a-d (p/d)

z

d’

0

1

0

z

z

Wire p

p 1

p 2

p 3

FT

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Path Sensitizing method (contd)

• Examples of sensitized i/ps for different gates

Two Four input z z^ z z z z z^ z z z z z z z z^ z z^ z z z

 - x 1 = • Can also determine these for other gates/components (e.g., XOR, XNOR, AOI, MUXes) - x 2 = - 1/ z - x 1 = - x 2 = - 1/ z - x 1 = - x 2 = - 1/ z - x 1 = - x 2 = - 1/ z - OR gate w/ s-a-0 OR gate w/ s-a-1 AND gate w/ s-a-0 AND gate w/ s-a- input 

• x 1 =
• x 2 =
• x 3 =
• x 4 = - x 1 = - x 2 = - x 3 = - x 4 = - 2/0 2/ - x 1 = - x 2 = - x 3 = - x 4 = - 2/ - x 1 = - x 2 = - x 3 = - x 4 = - 2/
  • x 1 =
  • x 2 =
  • x 3 =
  • x 4 = - 2/ - x 1 = - x 2 = - x 3 = - x 4 = - 2/ - x 1 = - x 2 = - x 3 = - x 4 = - 2/ - x 1 = - x 2 = - x 3 = - x 4 = - 2/

Path Sensitizing method (contd)

• Facts in fanout-free circuits (circuits in which each gate o/p feeds only 1 gate i/p or is a ckt o/p) and circuits w/ fanout (at least 1 gate o/p feeds > 1 gate i/ps): - For a given sensitized path, each wire along the path for p/d is also tested for a s-a-0 or s-a- fault as determined as follows: - For each wire w on the sensitized path, if logic value on w is z, then w is tested for w/d, otherwise (logic value on w is z’) it is tested for w/d’ - In Fig. 1 below, a test for 3/1 is also a test for 5/1 (the sensitized path is 3  5) - Thus fan-out free ckts can be tested for all possible single s-a-0 and s-a-1 faults by testing each primary input for s-a-0 and s-a-1 faults
• For fanout ckts, if the faulty point has a fanout, then its test will test all sensitized paths for that test; but all fanout paths from a fault may not be sensitized; so a faulty point’s test is not necessarily a test for all fanout paths - Thus should try to do multipath sensitization (either simultaneously or sequentially) if possible in fanout ckts. For sensitization of simultaneous paths, when the paths are reconvergent, then only under special cases (given later) will tests for the primary fault be tests for wires on these paths - If after tests for primary i/ps and their sensitized paths are determined for all possible faults, if some wires remain untested (because a path to them from primary i/ps cannot be sensitized), start the process from such wire(s) w/ the lowest level and find tests for them and all their sensitized paths

0

0

Forward trace

z

1

2 f 3

4 5 3/

x^ z 3 =

x 1 =X/ x 2 =0/X

Backward trace

Fig. 2: X nj^ is a test for p 1 /d, p 2 /d’, p 3 /d’, p 4 /d & p 5 /d’ on path1 and p 6 /d, p 7 /d’ & p 8 /d on path 2 Fig. 1: Test set for 3/1 & 5/1 = {000, 100, 010} if sensitized non-simultaneously

p 1 /d z z’ z’ z

z’ Test

X

jn p 2 /d’ p 3 /d’

p 4 /d p 5 /d’

d’

z (^) z’

z

p 6 /d p 7 /d’ p^8 /d

2 sensitized paths for p 1 /d

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Testing Circuits with Fanout

• Path sensitization: a) Multiple or single paths can be sensitized.
• Single path sensitized by TV 110; also a test for 4/0, 6/0.
• Further, the path is sensitized also for fault 2/1, except for a 0 needed now to be injected on wire 2. Thus if wire 2 is a primary i/p and does not provide any of the “other” i/ps to any gate on the senstitized path, then just by changing the corresponding i/p from 1 to 0, we get a test vector 100 for 2/1 (and 4/1, 6/1). (^) • Double path sensitized by TV 111
• However, this TV is not a test for 4/0, 5/0. E.g., consider fault 4/0. Since if 2 is non-faulty (nf)—we are testing for only single faults— wire 2 takes on value 1, which causes a 1 on wire 5, thus not sensitizing the path from wire 4 to the o/p 6.
• It is, however, a test for 6/0, since wire 6 occurs after the two paths reconverge (check out that 111 injects a 1 into 6)
• The corresp. double path sens. based test for 2/0 is 101 (as discussed above)
• TV 101 is also a test for 4/1, 5/1 and 6/1. E.g., consider 4/1. TV 101 injects a 0 into 4 (needed as the complement of the s-a-1 on 4), and on 5, needed for sensitizing the path from 4 to o/p 6

x 1 =

x 1 =

x 1 =

x 1 =

x 1 =

x 1 =

x 2 =

x 2 =

x 2 =

x 2 =

x 2 =

x 2 =

x 3 =

x 3 =

x 3 =

x 3 =

0

z z

z

0

1

4

5

6

x 1 = x 2 = x 3 =

2/

0

z

z z

1

1

4

5

6

• Another single path sensitized by TV 011; also a test for 5/0 & 6/0.
• Further, as in the top path sensitization, the vector 001 is a TV for 2/1 (and 5/1, 6/1)

x 1 =

x 2 =

x 3 =

2/

z

z z z

1

1

1

4

5

6

Reconvergence point/gate of the 2 fan-out paths

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Testing Circuits with Fanout---Multipath sensitization (contd)

• (c) If: (ii) the test is for p 1 /1, (ii) the multiple sensitized paths are reconvergent at an OR or NOR gate, and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1 /1 are also tests on subsequent wires p (^) j on these paths for pj/ d (d= 1, 0 for logic z, z’ resp. on pj) as shown above
• (d) The above two situations are completely reversed when condition (iii) changes to: (iii) the i/ps to the reconvergent gate are all z’ (the first 2 conditions remaining unchanged) as follows: Alternate of (b): All the p 1 /0 test(s) determined here are also test(s) for the intermediate wires s-a-0/ (based on z/z’ var, resp. on them) on the sensitized paths. This is b/c for an intermediate wire p (^) j, z’ on the other path(s) (the one(s) not containing p (^) j) = 0  path through pj via the reconv. OR/NOR gate is sensitized Alternate of (c): None of the the p 1 /1 test(s) determined here are tests on the intermediate wires on these paths before the reconvergent point (since z’ on the “other” path(s) = 1 thus not sensitizing the path through pj). They, are, however, tests for wires after the reconvergent gate.
  • (b) If: (i) the test is for p 1 /0, (ii) the multiple sensitized paths are reconvergent at an OR or NOR gate, and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1 /0 are not tests for any p (^) j/d (d= 0 or 1) for wires p (^) j on each path from p 1 to the reconverging gate. However, from the reconvergent point onwards, wires pk are also tested by the determined TV(s) for p 1 /0, based on whether the logic variable on wire p (^) k is z—the logic variable on p 1 —(tested for p (^) k /0) or z’ (tested for p (^) k /1)

p 1 / z z’ z’ z

z Test

X

jn p 2 p 3

p 4 p 5

1

z (^) z’ p 6 p 7

2 sensitized paths for p 1 /

z’ p 9 /0 (^) p 10 /

No tests for these wires

z

Reconvergence point/gate z^ or

p 8

p 1 / z z’^ z’ z

z Test

X

jn

p 5 /

0

z (^) z’ p 6 /

2 sensitized paths for p 1 /

z’ p 9 /1 p 10 /

Reconvergence point/gate p 7 /0 or

p 2 / p 3 /

p 4 /1 z

z

p 8 /

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Testing Circuits with Fanout---Multipath sensitization (contd)

• (f) If: (i) the test is for p 1 /0, (ii) the multiple sensitized paths are reconvergent at an AND or NAND gate, and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1 /0 are also tests on subsequent wires p (^) j on these paths for pj/d (d= 0, 1 for logic value z, z’, resp., on p (^) j) as shown above
• (g) The above two situations are completely reversed when condition (iii) changes to: (iii) the i/ps to the reconvergent gate are all z’ (the first 2 conditions remaining unchanged) as follows: Alternate of (e): All of the p 1 /1 test(s) determined here are test(s) for the intermediate wires s-a-0/1 (based on z/z’ var, resp. on them) on the sensitized paths. This is b/c for an intermediate wire p (^) j, z’ on the other path(s) (the one(s) not containing p (^) j) = 1  path through pj via the recconv. AND/NAND gate is sensitized Alternate of (f): None of the the p 1 /0 test(s) determined here are tests on the intermediate wires on these paths before the reconvergent point (since z’ on the “other” path(s) = 0, thus not sensitzing the path through pj). They, are, however, tests for wires after the reconvergent gate.
• (h) There cannot be simultaneously sensitized paths reconvergent on 2-i/p XOR/XNOR gates (the paths cannot be sensitized beyond such gates), & thus such gates are not considered here.
• (e) If: (i) the test is for p 1 /1, (ii) the multiple sensitized paths are reconvergent at an AND or NAND gate, and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1 /1 are not tests for any pj/d (d= 0 or 1) for wires p (^) j on each path from p 1 to the reconverging gate. However, from the reconvergent point onwards, wires p (^) k are also tested by the determined TV(s) for p 1 /1, based on whether the logic variable on wire p (^) k is z—the logic variable on p 1 —(tested for p (^) k /1) or z’ (tested for p (^) k /0)

p 1 / z z’^ z’ z

z Test

X

jn

p 5 /

1

z (^) z’ p 6 /

2 sensitized paths for p 1 /

z’ p 9 /0 (^) p 10 /

p 7 / z

p 8 /

p 2 / p 3 /

p 4 /0 (^) z

Reconvergence or point/gate

p 1 / z z’ z’ z

z Test

X

jn

p 2 p 3

p 4 p 5

0

z (^) z’ p (^6) p 7

2 sensitized paths for p 1 /

z’ p 9 /1 (^) p 10 /

No tests for these wires

z

Reconvergence or point/gate z

p 8

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Testing Circuits with Fanout

• Path sensitization (contd)
  • c) In other cases, single path sensitization will not work, and only multiple path will.

x 1 =

p/ z 1/z (either possible) General case

z x 2 =0 &

z

1

0->

Forward trace OK, but backward trace fails.

x 1 =

p/

z x 2 = z

0->1 Double path produces a test (11)

Not possible to get a 0, but may be possible get a z at an intermediate gate on the path being sensitized in the FT

z

• We need to try all possibilities (all single path sensitizations, all possible multi- path sensitizations) until a test is produced for the p/d fault we are considering
• There can be a large # of possibilities in complex circuits! Worst-case time can be v. high
• Adv over XOR method: A test for p/d automatically becomes tests for various faults along all single sensitized paths from p (do not have to compute them separately), and in some cases on simultaneously sensitized paths
• Disadv wrt XOR method: Not all tests for a p/d may be found (if we stop before exploring all paths from p, in all combinations of simultaniety), thus the fault table is not exhaustive, and the least-cost test set may not be found

Conflict!

0

1 0 1

1

1

1 0 1

1/z

Need to get a z instead of 1 for sensitization

Summary of P-S:

1 1

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Overview of Testing Phases

For each wire p and each d in {0,1} find tests for p/d by either: (a) the XOR method or (b) the path-sensitizing

Construct the fault table from the above tests (Note: the path-sensitizing method may not find all tests, though it will find at least 1 test for each p/d, if it exists)

Find a minimal test set from the fault table using a min-cost covering technique (e.g., similar to that used in the PIT part of single-function QM)

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