Lab Instructor: Miss Nosheen
Semester:2nd (2025)
Session: 2025
Date:
LAB-5 Implementation of XOR and XNOR Gates using
Basic and
NAND Gates
Nam
e
Reg.
No.
Mar
ks
Muhammad Rehan Ashraf 2025-cs-1278
CSC-105L โ Digital
Logic
Design
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Lab Instructor: Miss Nosheen
Semester: 2
nd
Session: 2025
Date:
LAB-5 Implementation of XOR and XNOR Gates using
Basic and
NAND Gates
Nam e Reg. No. Mar ks
Muhammad Rehan Ashraf 2025-cs-
CSC-105L โ Digital Logic
Design
5.1 Objectives The objectives of this experiment are: ๏ท To analyze the performance of XOR and XNOR gates ICs and draw their truth tables ๏ท To implement XOR and XNOR using basic gates only ๏ท To implement XOR and XNOR using NAND gates only 5.2 Theory In the previous labs, we saw that by using the three principal gates, the AND Gate, the OR Gate and the NOT Gate, we can build many other types of logic gate functions, such as a NAND Gate and a NOR Gate or any other type of digital logic functions. But there are two other types of digital logic gates which although they are not a basic gate as they are constructed by combining together other logic gates, their output Boolean function is important enough to be considered as complete logic gates. These two โhybridโ logic gates are called the Exclusive-OR (Ex-OR) Gate and its complement the Exclusive-NOR (Ex-NOR) Gate.
5.2.1 XOR Gate
A 2-input OR gate, if A = โ1โ, OR B = โ1โ, OR BOTH A + B = โ1โ then the output from the digital gate must also be at a logic level โ1โ and because of this, this type of logic gate is known as an Inclusive-OR function. The logic gate gets its name from the fact that it includes the case of Q = โ1โ when both A and B = โ1โ. If, however, a logic output โ1โ is obtained when ONLY A = โ1โ or when ONLY B = โ1โ but NOT both together at the same time, giving the binary inputs of โ01โ or โ10โ, then the output will be โ1โ. This type of gate is known as an Exclusive-OR function or more commonly an Ex-Or function for short. This is because its Boolean expression excludes the โOR BOTHโ case of Q = โ1โ when both A and B = โ1โ. In other words, the output of an Exclusive-OR gate ONLY goes โHIGHโ when its two input terminals are at โDIFFERENTโ logic levels with respect to each other. An odd number of logics โ1โsโ on its inputs gives a logic โ1โ at the output. These two inputs can be at logic level โ1โ or at logic level โ0โ giving us the Boolean expression of: Q = (A โ B) = A.B + A.B The Exclusive-OR Gate function, or Ex-OR for short, is achieved by combining standard logic gates together to form more complex gate functions that are used extensively in building arithmetic logic circuits, computational logic comparators and error detection circuits. The two-input โExclusive-ORโ gate is basically a modulo two adders, since it gives the sum of two binary numbers and as a result are more complex in design than other basic types of logic gate. The truth table, logic symbol and implementation of a 2-input Exclusive-OR gate is shown in Figure 5.1. Figure 5.1 2-input Ex-OR gate.
Figure 5.4 2-input Ex-NOR gate The Ex-NOR function is a combination of different basic logic gates Ex-OR and a NOT gate, and by using the 2-input truth table above, we can expand the Ex-NOR function to: Q = A โ B = (A.B) + (A.B) which means we can realize this new expression using the following individual gates. Figure 5.5 2-input Ex-OR gate plus a NOT gate The Exclusive-NOR Gate, also written as: โEx-NORโ or โXNORโ, function is achieved by combining standard/basic gates together to form more complex gate functions and an example of a 2-input Exclusive-NOR gate is given in Figure 5.6. Figure 5.6 Ex-NOR gate equivalence circuit One of the main disadvantages of implementing the Ex-NOR function above is that it contains three different types of logic gates the AND, NOT and finally an OR gate within its basic design. One easier way of producing the Ex-NOR function from a single gate type is to use NAND gates as shown in Figure 5.7. Figure 5.7 Ex-NOR Function implementation using NAND gates
5.3 Equipment ๏ท DC Power Source / Power Supply ๏ท Prototype Development Board ๏ท Connecting Wires 5.4 Components ๏ท ICs (7400, 7404, 7408, 7432, 7486, 74266) ๏ท 330 ฮฉ / 1 kฮฉ resistor ยผ watt Measured: 328 ฮฉ ๏ท LEDs 5.5 ICs Pin Diagrams Figure 5.8 2-input Logic XOR Gate IC Pin Diagram 5.6 Procedu re Figure 5.9 2-input Logic XNOR Gate IC Pin Diagram
- Place the development board gently on the observation table.
- Fix the IC which is under observation between the half shadow line of breadboard, so there is no shortage of voltage.
- Connect the wire to the main voltage source (Vcc) whose another end is connected to last pin of the IC (14 place from the notch).
- Connect the ground of IC (7th place from the notch) to the ground terminal of supply/kit.
Table 5.3 Observation of XOR implementation using Basic Gates
Input 1 Input 2 A+B A.B (A.B)โ (A+B).(A.B)โ
Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State 0 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 0 1 0 1 1 Table 5.4 Observation of XOR implementation using NAND Gates
Input 1 Input 2 C D E (Aโ.B)+(A.Bโ)
Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1
Table 5.5 Observation of XNOR implementation using Basic Gates
Input 1 Input 2 Aโ Bโ A.B Aโ.Bโ (A.B)+(Aโ.Bโ)
Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 Table 5.6 Observation of XNOR implementation using NAND Gates
Input 1 Input 2 Aโ Bโ (Aโ.Bโ)โ (A.B)โ (A.B)+(Aโ.Bโ)
Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 0 5.9 Results Table 5.7 Truth table of XOR
Input 1 Input 2 Output
Ans: When any ONE input of an XOR gate is HIGH (logic 1) and the other is LOW (logic 0), the output is HIGH (logic 1). However, if BOTH inputs are HIGH simultaneously, the output is LOW (logic 0). XOR outputs HIGH only when the inputs are DIFFERENT. So a single HIGH input gives output = 1, but two HIGH inputs give output = 0.
- When any of the input of XNOR gate is low, what would be the output? Ans: When any ONE input of an XNOR gate is LOW (logic 0) and the other is HIGH (logic 1), the output is LOW (logic 0). XNOR outputs HIGH (1) only when both inputs are the SAME (both 0 or both 1). When inputs are different (one low, one high), the output is LOW (0). 5.11Conclusion In this lab, we analyzed the XOR (IC 7486) and XNOR (IC 74266) gates and verified their truth tables experimentally. We successfully implemented XOR and XNOR functions using basic gates (AND, OR, NOT) and using NAND gates only. The 4-NAND-gate implementation of XOR and the 5-NAND-gate implementation of XNOR were verified to produce correct outputs for all input combinations. Results confirmed that XOR outputs HIGH only when inputs differ, while XNOR outputs HIGH only when inputs are the same. Both functions can be efficiently realized using universal NAND gates alone. 5.12Home Assignment Replicate the experiment through Verilog/proteus and submit the screenshots of software implementation in the form of brief technical report (5.13 Lab Report). Report must include the implementation of XOR and XNOR gates using lowest number of gates, basic gates only and universal gates only. Also include the pictures of hardware implementation. Home Assignment Report: XOR and XNOR Gate Implementation
1. Objective
This report presents the Verilog-based simulation of XOR and XNOR gates using three approaches: (1) minimum number of gates, (2) basic gates only (AND, OR, NOT), and (3) universal gates only (NAND gates). Truth tables are verified for all implementations.
2. XOR Gate Implementation
2.1 Minimum Gate Implementation (4 NAND Gates) The XOR function can be implemented using only 4 NAND gates. This is the minimum gate count for XOR using a single gate type. The Boolean derivation is: A XOR B = NAND(NAND(A, NAND(A,B)), NAND(B, NAND(A,B))) Verilog Code โ XOR using 4 NAND Gates: module xor_4nand(input A, B, output Y);
wire C, D, E; nand(C, A, B); // Gate 1: C = NAND(A,B) nand(D, A, C); // Gate 2: D = NAND(A,C) nand(E, B, C); // Gate 3: E = NAND(B,C) nand(Y, D, E); // Gate 4: Y = NAND(D,E) = A XOR B endmodule // Testbench module tb_xor_4nand; reg A, B; wire Y; xor_4nand uut(.A(A),.B(B),.Y(Y)); initial begin $monitor("A=%b B=%b Y=%b", A, B, Y); A=0;B=0; #10; A=0;B=1; #10; A=1;B=0; #10; A=1;B=1; #10; $finish; end endmodule Simulation Output (Truth Table Verification): A=0, B=0 โ Y=0 (correct) | A=0, B=1 โ Y=1 (correct) | A=1, B=0 โ Y=1 (correct) | A=1, B=1 โ Y=0 (correct) 2.2 XOR Using Basic Gates Only (AND, OR, NOT) Boolean expression: Y = AโB + ABโ = (A+B).(Aโ+Bโ) = (A+B).NAND(A,B). Implemented using AND, OR, and NOT gates as verified in Table 5.3. Verilog Code โ XOR using Basic Gates: module xor_basic(input A, B, output Y); wire An, Bn, t1, t2; not(An, A); // NOT gate: An = A' not(Bn, B); // NOT gate: Bn = B' and(t1, A, Bn); // AND gate: t1 = A.B' and(t2, An, B); // AND gate: t2 = A'.B or(Y, t1, t2); // OR gate: Y = A.B' + A'.B endmodule
3. XNOR Gate Implementation
3.1 Minimum Gate Implementation (5 NAND Gates) XNOR = NOT(XOR). Using the 4-NAND XOR and adding one more NAND gate as inverter (by tying both inputs together) gives XNOR in 5 NAND gates total. Boolean expression: A XNOR B = AB + AโBโ Verilog Code โ XNOR using 5 NAND Gates: module xnor_5nand(input A, B, output Y); wire C, D, E, Xor_out; nand(C, A, B); // Gate 1 nand(D, A, C); // Gate 2 nand(E, B, C); // Gate 3 nand(Xor_out, D, E); // Gate 4: XOR output nand(Y, Xor_out, Xor_out); // Gate 5: NOT(XOR) = XNOR endmodule Simulation Output (Truth Table Verification): A=0, B=0 โ Y=1 (correct) | A=0, B=1 โ Y=0 (correct) | A=1, B=0 โ Y=0 (correct) | A=1, B=1 โ Y=1 (correct) 3.2 XNOR Using Basic Gates Only (AND, OR, NOT) Boolean expression: Y = AB + AโBโ. Requires 2 NOT gates, 2 AND gates, and 1 OR gate ( gates total). Verified in Table 5.5. Verilog Code โ XNOR using Basic Gates: module xnor_basic(input A, B, output Y); wire An, Bn, t1, t2; not(An, A); // An = A' not(Bn, B); // Bn = B' and(t1, A, B); // t1 = A.B and(t2, An, Bn); // t2 = A'.B' or(Y, t1, t2); // Y = A.B + A'.B' = XNOR endmodule
4. XOR and XNOR Using Universal (NOR) Gates
As required by Analysis Question 2, XOR can also be implemented using NOR gates (universal gates other than NAND). The implementation uses 5 NOR gates as verified in the Analysis section. Verilog Code โ XOR using 5 NOR Gates:
Assessment Rubrics CSC-105L โ Digital Logic Design โ Lab 05
Name: Muhammad Rehan Ashraf Reg. No.: _ 2025 -CS- 1278
Method: Lab reports, viva, and instructor observation during lab sessions. Outcome Assessed:
- Ability to conduct experiments and projects, analyze and interpret the acquired data, and synthesize information to derive valid conclusions for digital logic circuits. (P2) (PLO โ 04)
- Ability to students will be able to demonstrate the implementation of digital logic circuits using Verilog simulations through modern tools. (P2) (PLO โ 05).
- Ability to contribute effectively and ethically as a team member towards the completion of labs and semester projects. (A2) (PLO โ 09).
- Ability to report and explain their project, experimental results, and findings effectively in written as well as in oral communication. (C2) (PLO โ 10). Performance Meets expectation (4-5) Lacking in expectation (3-2) Does not meet expectation (1-0) Marks
- Conducting Experiment [1] Focused attention on the experiment. Does proper calibration of equipment, carefully examines equipment and build circuits through relevant components, and ensures smooth operation and process. Focus was lost on several occasions. Calibrates equipment, examines equipment, and build circuits through relevant components, and operates the equipment with minor error. Students were hostile about participating or unable to do so. Or unable to calibrate appropriate equipment and build circuits through relevant components, and equipment operation is substantially wrong.
- Data Collection and Analysis [1] Accurately conducts simple computations and statistical analysis using collected data; correlates experimental results to known theoretical values; accounts for measurement errors and parameters that affect experimental results. Conducts simple computations and statistical analysis using collected data with minor error; reasonably correlates experimental results to known theoretical values; attempts to account for measurement errors and parameters that affect. experimental results. Unable to conduct simple statistical analysis on collected data; no attempt to correlate experimental results with known theoretical values; incapable of explaining measurement errors or parameters that affect the experimental results.
- Realization [1] Able to interpret the lab all-important results and data comparisons correctly; good understanding of labs is conveyed. Able to interpret the lab some of results and data comparisons correctly; fair understanding of labs is conveyed. Unable to interpret the lab results and comparison of data, a lack of understanding of results. Or incorrect interpretation of data is conveyed.
- Modern Tool Usage [2] Use computer to replicate the circuits through Verilog simulations and collect data effectively. Uses computer to replicate the DLD circuits through Verilog simulations and collect data with minor errors. Does not know how to use computer for the replication of DLD circuits through Verilog simulations and collect data.
- Teamwork [3] Actively engages in lab and cooperates with other group members. Also complete the labs and submissions in an effective manner and adhering to ethical values. Cooperates with other group members in a reasonable manner for the conduct of the lab and complete the labs in an effective manner as well as ethically. Distracts or discourages other group members from conducting the experiment and effective and ethical submission.
- Lab Report [4] The report illustrates an accurate and thorough understanding of scientific concepts underlying the lab and includes the experimental results and findings flawlessly or with some mistakes. All figures, graphs, tables are correctly drawn, are numbered and contain titles/captions or with few formatting mistakes. The report illustrates a limited understanding of scientific concepts underlying the lab and includes the experimental results and findings with major deficiencies. Most figures, graphs, tables OK, some still missing some important or required features. The report illustrates inaccurate understanding of scientific concepts underlying the lab or did not submit the lab report on time or/and having major deficiencies. Figures, graphs, tables contain errors or are poorly constructed, have missing titles, captions or numbers, units missing or incorrect, etc.
Total
Lab Instructor:
Name: ______________________ Signature:
Date: