School of Electrical Engineering and Computer Science
National University of Sciences & Technology (NUST)
Home Assignment No-4[CLO3]
Subject: Digital Logic Design Marks: 50
Course: BEE-10CD Issue: 07 Nov 2019
Teacher: Engr. Arshad Nazir Due on: 15 Nov 2019
Note: (10:00 AM)
Attempt the given problem set in a sequential order. Show all the design steps.
Make an index showing summary of the problems solved with page numbers and also
specify the missing ones.
No late submissions will be accepted unless a prior approval from the teacher is
obtained under extremely genuine reasons. The assignments submitted after the due
date/time will be graded zero.
University has zero tolerance for plagiarism and serious penalties apply. All assignments
found mutually copied will be marked zero.
The students will submit a certificate with the assignment work stating the originality of
their efforts and no copying from others.
Five marks are reserved for neat and clean work, table of contents, and certificate to be
attached with the assignment work.
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Problem No-1 Design a circuit that either Adds 5 or subtracts 5 from a 4-bit binary
number N. Let the inputs N3, N2, N1, N0 represent N. The input K is a
control signal. The circuit should have outputs M3, M2, M1, M0, which
represent the 4-bit number M. When K=0, M=N+5. When K=1, M=N-5.
Assume that the inputs for which M>11112 or M˂02 will never occur.
a. Implement your design with one 4-bit Binary Adder, one Quad 2-1
Multiplexer and NOT gates as required.
b. Realize the functions M3, M2, M1, and M0 using Two-Level NOR-NOR
form. Use minimum number of NOR gates. Assume that double-rail
inputs are available.
c. Implement the function M3 with a 5:32 decoder constructed from four
3:8 decoders with enable input E, one 2:4 decoder, and an external
OR gate with a large fan-in.
d. Realize the function M2 with a single 4-to-1 MUX. Take N1, N0 as
selection inputs.
e. Implement the function M1 using a 1:32 De-multiplexer constructed
with 1:4 De-multiplexers and an external OR gate with a large fan-in.
f. Realize the function M0 with four three-state buffers, and one 2:4
decoder only. Take N1, N0 as decoder inputs.
Note: Use blocks for Decoders/De-multiplexers and Multiplexers (internal
schematics not required)
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“Good Luck”
