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Ex. No: Date:
STUDY OF ARCHITECTURE OF DIGITAL SIGNAL PROCESSOR
AIM:
To study the Architecture of TMS320VC67XX DSP processor.
ARCHITECTURE
The 67XX DSPs use an advanced, modified Harvard architecture that maximizes processing power by maintaining one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit- manipulation operations that can all be performed in a single machine cycle. Also included are the control mechanisms to manage interrupts, repeated operations, and function calls.
mode bit (SXM) of ST1. Additional shift capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention operations
5. Multiplier/Adder The multiplier / adder perform 17-bit 2s-complement multiplication with a 40- bit accumulation in a single instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed/unsigned input control, fractional control, a zero detector, a rounder (2s-complement), overflow/saturation logic, and TREG. The multiplier has two inputs: one input is selected from the TREG, a data memory operand, or an accumulator; the other is selected from the program memory, the data memory, an accumulator, or an immediate value. The fast on-chip multiplier allows the C67XX to perform operations such as convolution, correlation, and filtering efficiently. In addition, the multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and in implementing symmetrical and least mean square (LMS) filters, which are required for complex DSP algorithms. 6. Compare, Select, and Store Unit (CSSU) The compare, select, and store unit (CSSU) performs maximum comparisons between the accumulator’s high and low words, allows the test/control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory. The CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware. 7. Program Control Program control is provided by several hardware and software mechanisms: The program controller decodes instructions, manages the pipeline, stores the status of operations, and decodes conditional operations. Some of the hardware elements included in the program controller are the program counter, the status and control register, the stack, and the address-generation logic. Some of the software mechanisms used for program control includes branches, calls, and conditional instructions, are peat instruction, reset, and interrupt. The C67XX supports both the use of hardware and software interrupts for
program control. Interrupt service routines are vectored through a re-locatable interrupt vector table. Interrupts can be globally enabled / disabled and can be individually masked through the interrupt mask register (IMR). Pending interrupts are indicated in the interrupt flag register (IFR). For detailed information on the structure of the interrupt vector table, the IMR and the IFR, see the device-specific data sheets.
8. Status Registers (ST0, ST1) The status registers, ST0 and ST1, contain the status of the various conditions and modes for the ‟ 67 XX devices. ST 0 contains the flags (OV, C, and TC) produced by arithmetic operations and bit manipulations in addition to the data page pointer (DP) and the auxiliary register pointer (ARP) fields. ST contains the various modes and instructions that the processor operates on and executes. 9. Auxiliary Registers (AR0–AR7) The eight 16-bit auxiliary registers (AR0–AR7) can be accessed by the central arithmetic logic unit (CALU) and modified by the auxiliary register arithmetic units (ARAUs). The primary function of the auxiliary registers is generating 16-bit addresses for data space. However, these registers also can act as general-purpose registers or counters. 10. Temporary Register (TREG) The TREG is used to hold one of the multiplicands for multiply and multiply/accumulate instructions. It can hold a dynamic (execution-time programmable) shift count for instructions with a shift operation such as ADD, LD, and SUB. It also can hold a dynamic bit address for the BITT instruction. The EXP instruction stores the exponent value computed into the TREG, while the NORM instruction uses the TREG value to normalize the number. For ACS operation of Viterbi decoding, TREG holds branch metrics used by the DADST and DSADT instructions. 11. Transition Register (TRN) The TRN is a 16-bit register that is used to hold the transition decision for the path to new metrics to perform the Viterbi algorithm. The CMPS (compare, select, max, and store) instruction updates the contents of the TRN based on the comparison between the accumulator high word and the accumulator low word. 12. Stack-Pointer Register (SP)
identified. Ex. No: Date: MAC OPERATION USING VARIOUS ADDRESSING MODES AIM To Study the various addressing modes of TMS320C5416 XX DSP processor. THEORY: Addressing Modes the TMS320C67XX DSP supports three types of addressing modes that enable flexible access to data memory, to memory-mapped registers, to register bits, and to I/O space: The absolute addressing mode allows you to reference a location by supplying all or part of an address as a constant in an instruction. The direct addressing mode allows you to reference a location using an address offset. The indirect addressing mode allows you to reference a location using a pointer. Each addressing mode provides one or more types of operands. An instruction that supports an addressing-mode operand has one of the following syntax elements listed below. Baddr When an instruction contains Baddr, that instruction can access one or two bits in an accumulator (AC0–AC3), an auxiliary register (AR0–AR7), or a temporary register (T0– T3). Only the register bit test/set/clear/complement instructions support Baddr. As you write one of these instructions, replace Baddr with a compatible operand. Cmem When an instruction contains Cmem, that instruction can access a single word ( bits)of data from data memory. As you write the instruction, replace Cmem with a compatible operand. Lmem When an instruction contains Lmem, that instruction can access a long word (32 bits) of data from data memory or from a memory-mapped registers. As you write the instruction, replace Lmem with a compatible operand. Smem When an instruction contains Smem, that instruction can access a single word ( bits) of data from data memory, from I/O space, or from a memory-mapped register. As you write the instruction, replace Smem with a compatible operand. Xmem and Ymem When an instruction contains Xmem and Ymem, that instruction can perform two
simultaneous 16-bit accesses to data memory. As you write the instruction, replace Xmem and Ymem with compatible operands. Absolute Addressing Modes k16 absolute This mode uses the 7-bit register called DPH (high part of the extended data page register) and a 16-bit unsigned constant to form a 23-bit data space address. This mode is used to access a memory location or a memory-mapped register. k23 absolute This mode enables you to specify a full address as a 23-bit unsigned constant. This mode is used to access a memory location or a memory-mapped register. I/O absolute This mode enables you to specify an I/O address as a 16-bit unsigned constant. This mode is used to access a location in I/O space. Direct Addressing Modes DP direct This mode uses the main data page specified by DPH (high part of the extended data page register) in conjunction with the data page register (DP).This mode is used to access a memory location or a memory-mapped register. SP direct This mode uses the main data page specified by SPH (high part of the extended stack pointers) in conjunction with the data stack pointer (SP). This mode is used to access stack values in data memory. Register-bit direct This mode uses an offset to specify a bit address. This mode is used to access one register bit or two adjacent register bits. PDP direct This mode uses the peripheral data page register (PDP) and an offset to specify an I/O address. This mode is used to access a location in I/O space. The DP direct and SP direct addressing modes are mutually exclusive. The mode selected depends on the CPL bit in status register ST1_67: 0 DP direct addressing mode 1 SP direct addressing mode The register-bit and PDP direct addressing modes are independent of the CPL bit. Indirect Addressing Modes You may use these modes for linear addressing or circular addressing. AR indirect This mode uses one of eight auxiliary registers (AR0–AR7) to point to data. The way the CPU uses the auxiliary register to generate an address depends on whether you
Ex. No: Date: ADDITION OF TWO NUMBERS AIM: To write a machine language program by using DSP Kit to add two numbers. ALGORITHM: Step1: Load the data page. That is define the current active page. Step2: Load accumulator with data from a memory location in the current active page. Step3: Add a data from another memory location with the data in the accumulator. Step4: Store the data from the accumulator to another memory location in the current active page. Step5: Stay in the loop. PROCEDURE:
- Open Code Composer Studio v4.
- To create the New Project Project→ New (File Name. pjt, Eg: vvits.pjt)
- To create a Source file File →New→ Type the code (Save & give file name, Eg: sum.asm).
- To Add Source files to Project Project→ Add files to Project sum.asm COMPILE:
- To Compile: Project→ Compile
- To Rebuild: project → rebuild, Which will create the final .out executable file. ( Eg. vvit.out).
- Procedure to Lode and Run program: Load the Program to DSK: File→ Load program →vvit.out To Execute project: Debug → Run PROGRAM:
. MMREGS
. TEXT
START:
LDP #100H ; Load the current active data page. LACC 0H ; Load the accumulator with a data from data page. ADD 1H ; Add a data in data page with the data in accumulator. SACL 5H ; Store the result in a memory location of the current data page. H: B H ; Stay inside loop. INPUT: 8000 - 0004H 8001 - 0004H OUTPUT 8005 - 0008H RESULT: Thus the given two numbers were added using the DSP Kit.
- To Rebuild: project → rebuild, Which will create the final .out executable file. ( Eg. vvit.out).
- Procedure to Lode and Run program: Load the Program to DSK: File→ Load program →vvit.out To Execute project: Debug → Run PROGRAM: . MMREGS . TEXT START: LDP #100H ; Load the current active data page. LT 01H ; Load the T register with a data from the current active data page. MPY 02H ; Multiply a data from a memory location in the current active data page with the data in T register. PAC ; Transfer the contents of product Register to accumulator. SACL 3H ; Store the result in the accumulator at a memory location in the current active data page. H: B H ; Stay inside loop. INPUT: 8000 - 0005H 8001 - 0002H OUTPUT 8005 - 000AH RESULT:
Thus the given two numbers were multiplied using the DSP Kit. Ex. No: Date: ONE AND TWO’S COMPLEMENTS AIM: To find one and two’s complement of the given numbers by using DSP Kit. ALGORITHM: Step1: Load the data page. That is define the current active page. Step2: Load the accumulator register with the data available from a memory location in the current active page. Step3: Complement the contents of accumulator. That is find one’s complements of the given data. Step4: Store the contents of accumulator in a memory location in the current active page. Step5: Add the data #1H with the contents of accumulator. That is find two’s complements of the given data. Step6: Store the contents of accumulator in a memory location in the current active page. Step7: Stay in the loop. PROCEDURE:
- Open Code Composer Studio v4.
- To create the New Project Project→ New (File Name. pjt, Eg: vvits.pjt)
- To create a Source file
8007 - EFF
RESULT:
Thus one and two’s complement of the given number was found by using the DSP Kit. Ex. No: Date: WAVE FORM GENERATION -SQUAREWAVE AIM: To generate a square wave of suitable frequency using the given TMS 320 C50 Trainer Kit. PROCEDURE:
- Open Code Composer Studio v4.
- To create the New Project Project→ New (File Name. pjt, Eg: vvits.pjt)
- To create a Source file File →New→ Type the code (Save & give file name, Eg: sum.asm).
- To Add Source files to Project Project→ Add files to Project sum.asm COMPILE:
- To Compile: Project→ Compile
- To Rebuild: project → rebuild, Which will create the final .out executable file. ( Eg. vvit.out).
- Procedure to Lode and Run program: Load the Program to DSK: File→ Load program →vvit.out To Execute project: Debug → Run
ALGORITHM:
Step1: Load the current active data page. Step2: Load accumulator with data from a memory location in the current active page. Step3: Store the data from the accumulator to another memory location in the current active page. This data will decide the amplitude of the square wave. Step4: Repeat step5 for n number of times. Where n is defined as a repeat counter. This will decide the time period of the square wave. Step5: Output the data in memory location 0 thro’ DAC. Step6: Complement the contents of accumulator. That is find one’s complements of the given data. Step7: The process from step3 is repeated indefinitely to obtain the square wave. PROGRAM:
. MMREGS . TEXT START: LDP #100H ; Load the current active data page. LACC #0FFFH ; Load the accumulator with a data from data page. LOOP: SACL 0H ; Store the result in a memory location of the current data page. RPT #0FFFH ; Repeat the above instruction for ‘n’ number of times. OUT 0,04H ; Output the data thro’ DAC.
CMPL ; Complement the data in accumulator.
B LOOP ; Set a indefinite loop. .END ; End the program.
Which will create the final .out executable file. ( Eg. vvit.out).
- Procedure to Lode and Run program: Load the Program to DSK: File→ Load program →vvit.out To Execute project: Debug → Run ALGORITHM: Step1: The values of frequency, amplitude and temporary locations are set. Step2: Load the current active data page. Step3: Clear the location temp. That is load the data zero at the location defined as temp. Step4: Load auxiliary register (AR2) with the set frequency value. Step5: Output the data zero from temp location through DAC to CRO. Step6: Load the accumulator with the data from temp location. Step7: Add the set amplitude value to the accumulator value. Step8: Store the partial result in accumulator at the location indicated by temp. This partial result indicates the amplitude of the waveform after one addition of set amplitude value. Step9: Initialize auxiliary register (AR2). That is access the set frq value. Step10: Branch to step 5 till the value in AR2 decrease to zero. That is the loop will be repeated till the set frequency decrease to zero. Step11: Clear the accumulator. Step12: Store the data in accumulator at the location indicated by temp. This data will resemble the fall of saw tooth. Step13: Output the data zero from temp location through DAC to CRO. Step14: Set a indefinite loop. Step15: End the program.
PROGRAM:
. MMREGS
.TEXT
AMPLITUDE .SET 8 ; Set the amplitude as 8. FREQUENCY .SET 150 ; Set the frequency as 150. TEMP .SET 0 ; Set temp location as 0. Whenever we refer temp, it indicates 0 th^ line of current page.
START: ;
LDP #100H ; Load the current active data page. SPLK #0,TEMP ; Clear the location temp. CONT1: ; LAR AR2 ,#FREQUENCY ; Load auxiliary register (AR2) with frequency value. CONT: ; OUT TEMP, 04H ; Output the data from temp thro’ DAC. LACC TEMP ; Load the accumulator with the data from temp location. ADD #AMPLITUDE ; Add amplitude value to acc value. SACL TEMP ; Store the data in accumulator at the location indicated by temp. MAR ,AR2 ; Initialize auxiliary register (AR2). BANZ CONT,- ; Branch to step 5 till the value in AR2 decrease to zero. LACC #0H ; Clear the accumulator. SACL TEMP ; Store the data in accumulator at the location indicated by temp. OUT TEMP,04H ; Output the data from temp thro’ DAC. B CONT1 ; Set a indefinite loop. .END ; End the program. RESULT: Thus, the desired saw tooth wave was generated by using CRO and the result was verified. Ex. No: Date: DESIGN OF FIR FILTER AIM: To design a window based FIR LP filter for the following specifications. Filter type: LOW PASS Approximation type: HAMMING Filter order: 52 Sampling frequency: 45 Khz Cutoff frequency: 4 Khz PROCEDURE:
- Open Code Composer Studio v4.
- To create the New Project Project→ New (File Name. pjt, Eg: vvits.pjt)
