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Electrical Engineering 42/100 Department of Electrical Engineering and Computer Sciences Summer 2012 University of California, Berkeley Instructor: Tony Dear
Final Exam Solutions
- Diodes Have Capacitance?!?! Frustrated at how inaccurate all our linear diode models have been, John decides to cook up another one. The Zener diode below has a linear ON characteristic and a breakdown voltage VB like any other, but it is modeled as a capacitor CD when it is reverse-biased, or OFF.
iD
vD 1
OFF
BD
ON
(V)
(A)
Reverse-Bias (OFF)
vD
iD CD −^10
(a) (3 points) Let’s first analyze the diode in its forward-bias (ON) mode. What is its linear circuit equivalent in this region of operation? Label the directions of vD and iD.
0 .5 Ω^ 1 V
vD
iD
(b) (3 points) John attaches this diode to a circuit as shown below.
1 Ω
5 u(t) A 3 Ω
vD (t) iD
Evidently, the Zener diode is now reverse-biased. On the plot below, draw in the load line imme- diately after the current source turns on, i.e., t = 0+. Be sure to label slopes and intercepts; your plot need not be to scale.
iD
vD
(V)
(A)
5 u(t) A 3 Ω
vD (t) iD
(c) (3 points) Suppose the “capacitance” of the diode is CD = 1 μF (10−^6 F). What is the time constant τ associated with it?
The time constant is given by τ = RCD , where R is the Th´evenin resistance as seen by the diode/capacitor. Since the current source becomes an open, the 1 Ω resistor has no effect, and we simply have τ = RCD = (3 Ω)(1 μF) = 3 μs
(d) (6 points) Sketch the voltage vD (t) across the diode as a function of time. Label key values on the vD axis. Remember that a charging capacitor reaches about 63% of its final value after one time constant τ. Don’t forget to account for the diode’s breakdown region!
The “capacitor” naturally wants to exponentially charge up to the steady-state value, which is −15 V (obtained if you treat the capacitor as an open circuit). However, this voltage abruptly ends at −10 V, the breakdown voltage of the diode.
t
vD (t)
(^0) τ 2 τ 3 τ
− 5
− 10
− 15
vo(t)
v+(t) vL(t)
C RL
1 kΩ
1 kΩ
C
vin(t)
(b) (5 points) Find an expression for vo(t) in terms of v+(t) and vin(t).
Using KCL at the inverting input of the op amp along with SPC (v+ = v−), we obtain
v+ − vin 1 kΩ
v+ − vo 1 kΩ
vo(t) = 2v+(t) − vin(t)
(c) (5 points) We’re almost there! Given what you found above, sketch the voltage vL(t). Be sure to label peak or constant values. Remember that we don’t care about transient effects!
Notice that the output side of the op amp is simply a peak detector with the diode facing backwards. Assuming negligible discharge, vL(t) will keep constant at the minimum value of vo(t). According to our expression above, the minimum value is
vL(t) = vo,min = 2v+,min − vin,min = 2(−7) − (−5) = −9 V
vL(t)
t
3. FFFFFFFFUUUUUUUUUUU
Jerry is trying to design an amplifier for the hundredth time. This time, he has turned to MOSFETs, specifically the common-source configuration. He has pulled up the following NMOS specs and designed the circuit as follows.
VG +
vin(t)
RD = 1 kΩ
20 V
vo(t)
RS = 500 Ω
K = .01 A/V^2
Vto = 2 V
1 kΩ
(a) (10 points) Recall that the transconductance of the transistor is given by
gm = 2K(VGS − Vto) = 2
KIDS (1)
Given that Tony has demanded gm = 20 mS (0.02 S), find the necessary bias VG that should be applied at the gate to achieve this.
gm = .02 = 2
KIDS = 2
. 01 IDS ⇒ IDS = .01 A
VS = IDS RS = (.01 A)(500 Ω) = 5 V
gm = .02 = 2K(VGS − Vto) = 2(.01)(VG − 5 − 2) ⇒ VG = 8 V
(c) (8 points) Tony now insists that the gain be a function of the signal frequency. Jerry cleverly adds in a source capacitor as follows.
+ CS
VG
vin(t)
RD = 1 kΩ
20 V
vo(t)
RS = 500 Ω
K = .01 A/V^2
Vto = 2 V
1 kΩ
The gain of the amplifier now becomes a complex transfer function, given by
H(ω) =
Vo Vin
−gmRD 1 + gmZS
−gmRD 1 + gmRS
1 + jωRS CS 1 + jω (^) 1+RgSm^ CRSS
1 + jωRS CS 1 + jωRS CS / 10
Sketch the magnitude Bode plot for the transfer function. Be sure to label any cutoff frequencies and asymptotic magnitude values, as well as slopes. You may leave your plot labels in terms of RS CS for convenience. (Hint: 20 log 10 (2) = 6)
ω
|H(ω)|dB
6
26
1
RS CS
10
RS CS
- Introducing... the NYAN gate!
Dennis has finally perfected the NYAN gate and is ready to add it to the current repertoire of logic gates. Its logic gate symbol is shown below:
A
B
C
N
Unlike most other logic gates, the NYAN gate takes in exactly three inputs. The truth table showing all its possible input/output combinations is as follows:
A B C N 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0
(a) (2 points) Is the NYAN gate commutative? Briefly justify why or why not.
No, it is not. Observe that the order of inputs into the gate actually matters. For example, NYAN(0, 0, 1) 6 = NYAN(0, 1, 0).
(b) (6 points) Write the SOP Boolean expression for the output N in terms of the inputs A, B, and C. Simplify it into a sum of two terms only.
N = A B C + ABC + AB C + ABC
= A C(B + B) + AB(C + C)
= A C + AB
- The Final Countdown
The hours that you have left in EE42/100 are numbered, and you can’t wait to finish this exam and GTFO to party away your Friday night and what’s left of summer. But before you do so, you must help finish our timer circuit below to perform the final countdown.
J
K
Q 0
Q 0
Clk
Clk
J
K
Q 1
Q 1
Clk
Recall that the behavior of the JK flip flop is as follows:
Clk J K Qn+ 0 × × Qn 1 × × Qn ↑ 0 0 Qn ↑ 0 1 0 ↑ 1 0 1 ↑ 1 1 Qn
(a) (4 points) The output of this circuit is given by Q = (Q 1 Q 0 ) 2. Draw the state transition diagram for the given circuit above.
J
K
Q 0
Q 0
Clk
Clk
J
K
Q 1
Q 1
Clk
(b) (4 points) The first feature we want to add is the ability to pause the timer. Suppose we add in a new input P ; when P = 1, the timer keeps its current state and ignores the clock (Q should not reset to 0). Then when P = 0, the timer continues as usual. Given the original two flip flops below, make all the necessary connections to implement this new feature, using logic gates if necessary.
Clk
J
K
Q 1
Q 1
Clk
J
K
Q 0
Q 0
Clk
P
J
K
Q 0
Q 0
Clk
Clk
J
K
Q 1
Q 1
Clk
(d) (8 points) You may have noticed that our timer doesn’t have a very wide range, since it only has two bits of output. The last extension we want to do is to modify the timer so that it counts down from Q = 7. Make all the necessary connections to implement this new feature, using logic gates if necessary. (Notice that we have drawn in a third flip flop for you.)
Clk
J
K
Q 1
Q 1
Clk
J
K
Q 0
Q 0
Clk
J
K
Q 2
Q 2
Clk
