Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Directory, Protocol, Processors, Cache, Blocks, Fetch, Invalidate, Remote, Directory, Address
Typology: Slides
1 / 19
This page cannot be seen from the preview
Don't miss anything!
In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy)
Keep it simple(r):
No bus and don’t want to broadcast:
Typically 3 processors involved
Message type Source Destination Msg Content
Invalidate Home directory Remote caches A
Fetch Home directory Remote cache A
Fetch/Invalidate Home directory Remote cache A
Message type Source Destination Msg Content
Data value reply Home directory Local cache Data
Data write-back Remote cache Home directory A, Data
Write misses that were broadcast on the bus for snooping results in explicit invalidate & data fetch requests.
Note: on a write, a cache block is bigger, so need to read the full cache block
State machine for CPU requests for each memory block Invalid state if in memory
Fetch/Invalidate or Miss due to address conflict: send Data Write Back message to home directory
Invalidate or Miss due to address conflict: Invalid (^) (read/onlyShared )
Exclusive (read/writ e)
CPU Read
CPU Read hit
Send Read Miss message CPU Write: Send Write Miss msg to h.d.
CPU Write: Send Write Miss message to home directory
CPU read hit CPU write hit
Fetch: send Data Write Back message to home directory
State machine for Directory requests for each memory block Un-cached state if in memory Data Write Back: Sharers = {} (Write back block)
Uncached Shared (read only)
Exclusive (read/writ e)
Read miss: Sharers = {P} send Data Value Reply
Write Miss: send Invalidate to Sharers; then Sharers = {P}; send Data Value Reply msg
Write Miss: Sharers = {P}; send Data Value Reply msg
Read miss: Sharers += {P}; send Fetch; send Data Value Reply msg to remote cache (Write back block)
Read miss: Sharers += {P}; send Data Value Reply
Write Miss: Sharers = {P}; send Fetch/Invalidate; send Data Value Reply msg to remote cache docsity.com
Message sent to directory causes two actions:
Block is in Uncached state: the copy in memory is the current value; only possible requests for that block are:
Block is Shared state => the memory value is up- to-date; the read miss and write miss activities are:
Block is Exclusive:
current value of the block is held in the cache of the processor identified by the set Sharers (the owner)
three possible directory requests:
owner processor is replacing the block and hence must write it back, making memory copy up-to-date
the block is now Uncached, and the Sharer set is empty.
block has a new owner.
A message is sent to old owner causing the cache to send the value of the block to the directory from which it is sent to the requesting processor, which becomes the new owner.
Sharers is set to identity of new owner, and state of block is made Exclusive.
