Improving Cache Performance
Average memory access time gives
framework to optimize the cache
performance
The Average memory access time formula:
Average Memory Access time =
Hit Time + Miss Rate x Miss Penalty
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Improving Cache Performance-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture
This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Improving, Memory, Optimize, Framework, Memory, Cache, Performance, Merging, Priority, Buffers, Multilevel
Typology: Slides
2011/2012
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Improving Cache Performance
Average memory access time gives framework to optimize the cache performance The Average memory access time formula:
Average Memory Access time =
Hit Time + Miss Rate x Miss Penalty
Four General Options
1. Reduce the miss penalty,
2. Reduce the miss rate,
3. Reduce miss Penalty or miss rate via
Parallelism
4. Reduce the time to hit in the cache
1: Multilevel Caches (to reduce Miss Penalty)
This technique ignores the CPU but
concentrates on the interface between
cache and maim memory
Multiple levels of caches
Tradeoff between cache size (cache
effectiveness and cost (access time) a
small fastest memory is used as level- 1
cache
1: Multilevel Caches (Performance Analysis)
Average access Time is: Access Time (^) average = Hit Time (^) L1 + Miss Rate (^) L1 x Miss Penalty (^) L Where, Miss Penalty (^) L
= Hit Time L2 + Miss Rate L2 x Miss Penalty L
Therefore,
The Average memory access time
= Hit Time (^) L1 + Miss Rate (^) L1 x (Hit Time (^) L2 + Miss Rate (^) L2 x Miss Penalty (^) L2 )
1: Multilevel Caches (to reduce Miss Penalty)
Local miss rate
Global miss rate
1: Multilevel Caches (to reduce Miss Penalty)
Local Miss Rate: Measure of misses in a cache divided by the total number of misses in this cache. Global Miss Rate: Measure of the number of misses in the cache divided by the total number of memory access generated by the CPU
1: Multilevel Caches (to reduce Miss Penalty)
Example: Find the local and global miss rates,
the Average Memory Access Time and Average memory stall cycles per instruction, given that for 1000 reference with 40 misses in L1 cache and 20 in L2 Cache;
Assume:
- miss penalty for L2 cache-memory = 100 clock cycles
- hit time for L2 cache is 10 clock cycle
- Hit time for L1 cache is 1 Clock cycle
- Memory Reference per instruction = 1.
1: Multilevel Caches (to reduce Miss Penalty)
Solution:
Miss rate for either local or global
L1 cache is same = 4% [(40/1000)x100]
Local Miss Rate for L2 = 50% [20/40]
Global Miss Rate for L2 cache = 2% [(20/1000)x100]
Then
1: Multilevel Caches (to reduce Miss Penalty)
Average Memory Stalls per instruction (i.e., miss penalty) = Misses per instruction L1 x Hit Time L +Misses per instruction L2 x Miss Penalty L
For Memory references per instruction = 1. Misses per instruction for L1 = 40 x 1.5 = 60 per 1000 instructions Misses per instruction for L2 = 20 x 1.5 = 30 per 1000 instructions Average Memory Stalls per instruction = (60/1000) x10 + 30/1000) x 100 = 0.6 +3.0 = 3.6 clock cycles i.e., the average miss penalty using multi level caches reduces by a factor of 100/3.6 = 28 relative to the single level cache
1: Multilevel Caches (to reduce Miss Penalty)
Miss rate verses cache size for multilevel caches The miss-rate of single level cache verses size is plotted against the local and global miss rates of 2nd^ level cache using 32 KB 1st^ level cache – L unified cache is 2-way set associative with LRU replacement