Understanding Dynamic Networks: Crossbar Switches & Multistage Interconnection, Slides of Computer Architecture and Organization

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Dynamic Networks

What is Dynamic Network

• Dynamic Network is the network that can connect any input to any output by enabling or disabling some switches in the network
• Examples:
  • Shared Bus: The bus arbiter connects a processor to a memory
  • Crossbar: Consists of a lot of switching elements, which can be enabled to connect many inputs to many outputs simultaneously
  • Multistage Network: Consists of several stages of switches that are enabled to get connections
  • The nodes in static networks (like Mesh) also consist of dynamic crossbars

How do you build a crossbar

Io

I (^1)

I (^2)

I (^3)

I (^) o I 1 I 2 I 3 O 0 Oi O 2 O 3

N2 switches => Cost O(N2) Multiplexors are controlled from Time taken by the arbiter = O(N2) the arbiter/controller/scheduler**

From Control

Crossbar Contd.

• An NXN Crossbar allows all N inputs to be connected simultaneously to all N outputs
• It allows all one-to-one mappings, called permutations. No. of permutations = N!
• When two or more inputs request the same output, it is called CONFLICT. Only one of them is connected and others are either dropped or buffered
• When processors access memories through crossbar, this situation is called memory access conflicts
• Given p as the probability of request by a processor per cycle and assuming that each of N processors’ request is uniformly directed to all N memories, the average number of connections allowed per cycle, called Bandwidth (BW) is BW = N{1- (1-p/N)**N} – Derive this!!!

Problems with Input-Buffered

Switch

• FIFO Input buffers give rise to Head of the Line (HOL) problem
• Current routers employ a separate input queue for each output, called virtual output queue (VOQ)
• Then how to schedule the packets from different VOQ’s for transmission?

VOQ-based Input Buffered Switch

Output Buffered Switch

• How would you build a shared pool?

Control

Input Ports OutputPorts

OutputPorts

OutputPorts

OutputPorts

R

R

R

R

Output scheduling

• n independent arbitration problems?
  • static priority, random, round-robin
• simplifications due to routing algorithm?
• general case is max bipartite matching

Cross-bar

OutputPorts

R R R R

O

O

O

InputBuffers

Multistage interconnection

networks

0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111

1

1

0 Complexity: Omega Network Complexity O(Nlog 2 N) Self Routing:Of the destination. At each switch, the corresponding tag bit is checked. The source node generates a tag, which is binary equivalent

Input is connected to the lower output. If both inputs have either 0 or 1,If the bit is 0, the input is connected to the upper output. If it is 1, the It is a switch conflict. One of them is connected. The other one is rejected orbuffered at the switch (if it has buffer => buffered crossbar)

What is Shuffle?

000 001 010 011 100 101 110 111

000 001 010 011 100 101 110 111

000 001 010 011 100 101 110 111

000 001 010 011 100 101 110 111

**=

=

=

= =**

(a) Perfect shuffle (b) Inverse perfect shuffle

shuffle interconnection S(an-1 an-2 … a 1 a 0 ) = (an-2 an-3 … a 0 an-1 )

Self Routing

• A processor generates a tag that is binary equivalent of the destination
• MSB controls the leftmost stage and the lsb controls the rightmost stage of the Omega network. A small controller inside the 2 x 2 switch senses this bit and enables the connection
• If bit c (^) i = 0, the request is to the upper output; if it is 1, the request is to the lower output.
• Based on digit if switch size is greater than 2
• Network conflict - Select Round Robin
• Less Bandwidth than crossbar, but more cost effective
• What about QoS? Future research

Theorem: The Omega network is self

routing

Let source be (s (^) n-1sn-2 … s 2 … s 1 s 0 ) and destination be (d (^) n-1dn-2 … d 2 … d 1 d 0 ). Before Stage 1, the source is switched to the position (s (^) n-2sn-3 … s 1 … s 0 sn-1) due to perfect shuffle connection. After Stage 1 it is switched to (s (^) n-2sn-3 … s 1 … s 0 dn-1) as per the (n-1)th^ of the destination. Before 2nd^ stage of the switches, the source is connected to (s (^) n-3 … s 0 dn-1sn-2) as after 2 nd^ stage it becomes (s (^) n-3 … s 0 dn-1dn-2)

Example: SP

• 8-port switch, 40 MB/s per link, 8-bit phit, 16-bit flit, single 40 MHz clock
• packet sw, cut-through, no virtual channel, source-based routing
• variable packet <= 255 bytes, 31 byte fifo per input, 7 bytes per output, 16 phit links

P 0 P 1 P 2 P 3 P 15

E 0 E 1 E 2 E 3 E 15

Intra-Rack Host Ports

Inter-Rack External Switch Ports

16-node Rack

SwitchBoard

Multi-rack Configuration

Example: IBM SP vulcan switch

• Many gigabit ethernet switches use similar design without the cut-through

FIFO CRCcheck Routecontrol

FlowControl (^8 8) Deserializer 64

Input Port

RAM64x

InArb OutArb

Crossbar^ 8 x 8

CentralQueue FIFO CRCGen

FlowControl (^64) Serializer (^8 )

Ouput Port XBarArb

FIFO CRCcheck Routecontrol

FlowControl (^8 8) Deserializer

Input Port

°° °

64

°° ° FIFO CRC Gen

FlowControl Serializer^8

Ouput Port (^8) XBarArb

°° °

8