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Computer Science and Engineering Lab Experiments: Semester-wise Breakdown, Schemes and Mind Maps of Computer Networks

Christ UniversityComputer Networks

The topics and experiments to be covered in the computer science and engineering lab course during various semesters. Students are required to design, construct, and demonstrate the working of various circuits, including positive clipper double-ended clippers, ce amplifiers, cmos inverters, schmitt triggers, and multivibrators. They will also learn to simplify boolean expressions, design and develop verilog/vhdl codes for multiplexers, flip-flops, and counters, and build asynchronous counters using decade counter ics.

Typology: Schemes and Mind Maps

2014/2015

Uploaded on 08/14/2015

chethana
chethana 🇮🇳

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bg1
Course
B.E.
Branch
Computer Science and Engineering
Staff Name
Rekha V S, Vindhya N S,Jahnavi S
Subject
EC/LD Lab
Semester
3
Department
Computer Science and Engineering
Week No. Hours Date Topic to be Covered
1 3 06-08-2015 Experiment-1
2 3 13-08-2015 Experiment-1
3 3 20-08-2015 Experiment-2
4 3 27-08-2015 Experiment-3
5 3 03-09-2015 Experiment-4
6 3 10-09-2015 Experiment-5
8 3 01-10-2015 Experiment-6
9 3 08-10-2015 Experiment-7
10 3 29-10-2015 Experiment-8
pf3
pf4

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Download Computer Science and Engineering Lab Experiments: Semester-wise Breakdown and more Schemes and Mind Maps Computer Networks in PDF only on Docsity!

Course

Branch (^) Computer Sc

Staff Name (^) Rekha V S, V

Subject (^) E

Semester

Department (^) Computer Sc

Week No. Hours Date Topic to be Covered

1 3 06-08-2015 Experiment-

2 3 13-08-2015 Experiment-

3 3 20-08-2015 Experiment-

4 3 27-08-2015 Experiment-

5 3 03-09-2015 Experiment-

6 3 10-09-2015 Experiment-

8 3 01-10-2015 Experiment-

9 3 08-10-2015 Experiment-

10 3 29-10-2015 Experiment-

  • 12 3 05-11-2015 Experiment-9 &
  • 13 3 19-11-2015 Experiment-11&
  1. a. Design and implement a mod n (a<8) synchronous up counter using JK FF IC’s and demonstrate its working. b. Design and develop the verilog/VHDL code for mod 8 up counter simulate and verify its working. 10 a. Design and implement ring counter using 4-bit shift register and demonstrate its working. b. Design and develop the verilog /VHDL code for switched tail counter. Simulate and verify its working.

11. Design and implement asynchronous counter using decade counter IC to count up from

0 to n (n≤9) and demonstrate its working. 12

converter using Op-Amp. Determine its accuracy and

resolution.