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Question 1. Which law states that the sum of currents entering a node equals the sum leaving it? A) Ohm’s Law B) Kirchhoff’s Current Law C) Faraday’s Law D) Coulomb’s Law Answer: B Explanation: KCL asserts that total current at a junction is conserved, so the algebraic sum is zero. Question 2. In a semiconductor, the energy difference between the valence band and the conduction band is called the: A) Fermi level B) Bandgap energy C) Work function D) Electron affinity Answer: B Explanation: The bandgap is the energy required for an electron to move from the valence to the conduction band. Question 3. The phasor representation of a sinusoidal voltage of amplitude 10 V at 60° is: A) 10∠ 0 ° V B) 10∠ 60 ° V C) 10∠- 60 ° V D) 10∠ 90 ° V Answer: B Explanation: A phasor includes magnitude and phase; thus 10 V at 60° is 10∠ 60 °. Question 4. Which of the following is the Laplace transform of the unit step function u(t)?
A) 1/s B) s C) 1/(s+1) D) s/(s+1) Answer: A Explanation: L{u(t)} = ∫₀^∞ e^(-st) dt = 1/s. Question 5. For a series R-L circuit with resistance 10 Ω and inductance 0.1 H, the time constant τ equals: A) 0.01 s B) 0.1 s C) 1 s D) 10 s Answer: B Explanation: τ = L/R = 0.1 H / 10 Ω = 0.01 s (Oops, correct calculation: 0.1/10 = 0.01 s). Therefore answer should be A. Correct Answer: A Explanation: τ = L/R = 0.1 H / 10 Ω = 0.01 s. Question 6. A transformer with a primary of 120 V and a turns ratio of 1:5 will produce a secondary voltage of: A) 24 V B) 120 V C) 600 V D) 30 V Answer: C Explanation: V₂ = (N₂/N₁)·V₁ = 5·120 V = 600 V. Question 7. In a resistor-capacitor (RC) low-pass filter, the cutoff frequency f_c is given by: A) 1/(2πRC)
D) It can operate at any frequency. Answer: A Explanation: Infinite input impedance implies the input pins draw zero current. Question 11. In an inverting op-amp configuration, the voltage gain is – Rf/Rin. If Rf = 100 kΩ and Rin = 10 kΩ, the gain is: A) – B) –0. C) 10 D) 0. Answer: A Explanation: Gain = –Rf/Rin = –100 kΩ/10 kΩ = –10. **Question 12. Which logic gate implements the Boolean expression Y = A·B + ¬C? ** A) NAND B) NOR C) AND-OR D) XOR Answer: C Explanation: An AND-OR gate can directly realize A·B OR ¬C. Question 13. The truth table of a NAND gate yields a ‘0’ output only when: A) Both inputs are 0. B) Both inputs are 1. C) Either input is 0. D) Either input is 1. Answer: B Explanation: NAND is the complement of AND; only when both inputs are 1 does the output become 0.
Question 14. Using De Morgan’s theorem, the complement of (A + B)·C is: A) (¬A · ¬B) + ¬C B) (¬A + ¬B) · ¬C C) (¬A · ¬B) · ¬C D) (¬A + ¬B) + ¬C Answer: B Explanation: ¬[(A + B)·C] = ¬(A + B) + ¬C = (¬A·¬B) + ¬C. Wait, apply correctly: ¬[(A+B)·C] = ¬(A+B) + ¬C = (¬A·¬B) + ¬C. That matches option A? Option A is (¬A·¬B) + ¬C. So answer is A. Correct Answer: A Explanation: De Morgan’s gives ¬(X·Y)=¬X+¬Y and ¬(X+Y)=¬X·¬Y; thus the complement is (¬A·¬B)+¬C. Question 15. A 4-bit binary ripple-counter using JK flip-flops toggles on each clock pulse. The frequency at the MSB (Q3) is: A) f_clk / 2 B) f_clk / 4 C) f_clk / 8 D) f_clk / 16 Answer: D Explanation: Each stage divides frequency by 2; after 4 stages, division factor = 2⁴ = 16. Question 16. In a synchronous 4-bit binary counter, the propagation delay is primarily determined by: A) The ripple through each flip-flop. B) The longest combinational path from clock to Q output. C) The number of gates in the decoder. D) The supply voltage. Answer: B Explanation: Synchronous counters have all flip-flops triggered simultaneously; the critical path is the longest combinational logic from clock edge to output.
B) Direct C) Register D) Relative Answer: D Explanation: Relative addressing adds an offset to the program counter to locate the operand. Question 21. In UART communication, the term “baud rate” refers to: A) Number of bits transmitted per second. B) Number of symbols per second. C) Voltage level of the line. D) Clock frequency of the microcontroller. Answer: B Explanation: Baud rate is the number of signal changes (symbols) per second; for binary signaling, it equals bits per second. Question 22. The SPI protocol uses how many dedicated lines for full-duplex communication between master and slave? A) 2 B) 3 C) 4 D) 5 Answer: C Explanation: SPI typically uses MOSI, MISO, SCLK, and SS (chip-select), totaling four lines. Question 23. In a successive-approximation ADC, the conversion time is proportional to: A) 2ⁿ clock cycles, where n is resolution. B) n clock cycles. C) 1/n clock cycles.
D) log₂(n) clock cycles. Answer: B Explanation: An n-bit SAR ADC requires n comparison cycles to converge. Question 24. Amplitude Modulation (AM) transmits information by varying which carrier property? A) Frequency B) Phase C) Amplitude D) Pulse width Answer: C Explanation: AM changes the amplitude of the carrier proportional to the message signal. Question 25. In Frequency Shift Keying (FSK), binary ‘1’ and ‘0’ are represented by: A) Two different amplitudes. B) Two different phases. C) Two different frequencies. D) Two different pulse widths. Answer: C Explanation: FSK uses two distinct carrier frequencies for the two binary states. Question 26. The Z-transform of the discrete-time unit step sequence u[n] is: A) 1/(1-z⁻¹) B) z/(z-1) C) 1/(1-z) D) z⁻¹/(1-z⁻¹) Answer: B Explanation: Z{u[n]} = Σ_{n=0}^{∞} z⁻ⁿ = 1/(1-z⁻¹) = z/(z-1).
A) DIAC
B) SCR
C) TRIAC
D) GTO
Answer: B Explanation: A Silicon Controlled Rectifier (SCR) conducts only when its gate receives a triggering pulse. Question 31. A buck converter steps down voltage. Its duty cycle D is defined as: A) V_out / V_in B) V_in / V_out C) √(V_out / V_in) D) (V_out – V_in)/V_in Answer: A Explanation: For an ideal buck, V_out = D·V_in, so D = V_out / V_in. Question 32. In a boost converter, the inductor stores energy during the switch-on interval. The voltage conversion ratio V_out/V_in equals: A) 1 / (1-D) B) 1-D C) D D) 1 + D Answer: A Explanation: Ideal boost converter: V_out = V_in / (1-D). Question 33. The Wheatstone bridge is used to measure: A) Capacitance only B) Inductance only C) Unknown resistance precisely D) Power factor
Answer: C Explanation: By balancing the bridge, the unknown resistor can be calculated from known ratios. Question 34. An oscilloscope’s vertical sensitivity is set to 2 V/div and the displayed waveform spans 4 divisions peak-to-peak. The peak-to-peak voltage is: A) 2 V B) 4 V C) 8 V D) 16 V Answer: C Explanation: V_pp = 2 V/div × 4 div = 8 V. Question 35. A thermocouple generates a voltage because of: A) Photoelectric effect B) Seebeck effect C) Hall effect D) Peltier effect Answer: B Explanation: The Seebeck effect creates a voltage proportional to temperature difference between two metals. Question 36. In a strain gauge, the change in resistance is proportional to: A) Temperature only B) Applied force only C) Mechanical strain (deformation) D) Magnetic field strength Answer: C Explanation: Strain gauges convert mechanical deformation into a resistance change.
D) Infinite Answer: C Explanation: The emitter follower presents a high input impedance due to the base-emitter junction being forward-biased. Question 41. The cutoff frequency of an LC series resonant circuit is: A) 1/(2πRC) B) 1/(2π√(LC)) C) √(L/C) D) 2π√(LC) Answer: B Explanation: Resonant frequency f₀ = 1/(2π√(LC)). Question 42. The Q-factor of a series resonant circuit is defined as: A) ω₀L/R B) R/(ω₀L) C) ω₀RC D) 1/(ω₀RC) Answer: A Explanation: Q = ω₀L / R for a series RLC circuit. Question 43. In a digital comparator circuit, if the non-inverting input is higher than the inverting input, the output is: A) Logic 0 B) Logic 1 C) Undefined D) Oscillatory Answer: B Explanation: A comparator output follows the sign of (V⁺ – V⁻); higher non-inverting input yields high output.
Question 44. A Schmitt trigger improves noise immunity by: A) Providing a single threshold voltage. B) Using two distinct threshold voltages (hysteresis). C) Amplifying the input signal. D) Filtering high-frequency components. Answer: B Explanation: Hysteresis creates separate upper and lower switching thresholds, reducing false triggering. Question 45. The Boolean expression for a 2-to-4 decoder with enable (EN) is: A) Y₀ = EN·¬A·¬B, Y₁ = EN·¬A·B, Y₂ = EN·A·¬B, Y₃ = EN·A·B B) Y₀ = EN·A·B, Y₁ = EN·A·¬B, Y₂ = EN·¬A·B, Y₃ = EN·¬A·¬B C) Y₀ = ¬EN·¬A·¬B, … D) Y₀ = EN + ¬A + ¬B, … Answer: A Explanation: Each output is asserted when EN is high and the address inputs match the binary code. Question 46. In a synchronous 4-bit binary up-counter built from JK flip-flops, what J and K inputs are required for each flip-flop? A) J=K=Q (previous stage) B) J=K=1 for all C) J=K=Qq (previous stage) D) J=K=0 for all Answer: B Explanation: To toggle on every clock, JK inputs are tied high (logic 1) for each stage; synchronous gating ensures correct toggling. Question 47. The maximum power transfer theorem states that maximum power is delivered to a load when: A) Load resistance equals source resistance.
Explanation: The Gaussian pulse achieves the minimum time-bandwidth product, approximately 0.44. Question 51. Which of the following is a characteristic of an ideal diode? A) Constant forward voltage drop. B) Zero resistance in reverse bias. C) Zero voltage drop when forward-biased and infinite resistance when reverse-biased. D) Linear I-V relationship. Answer: C Explanation: An ideal diode conducts perfectly in forward bias (zero drop) and blocks completely in reverse bias (infinite resistance). Question 52. In a CMOS inverter, the static power consumption is mainly due to: A) Leakage current. B) Switching current. C) Both A and B equally. D) None; CMOS consumes zero static power. Answer: A Explanation: In steady state, only leakage currents flow; ideal CMOS has negligible static power. Question 53. The Miller effect in an inverting amplifier primarily increases: A) Input resistance. B) Output resistance. C) Effective input capacitance. D) Bandwidth. Answer: C Explanation: The Miller multiplication makes the feedback capacitance appear larger at the input, reducing bandwidth.
Question 54. A 555 timer configured in astable mode produces a square wave. The frequency is inversely proportional to: A) (R1 + R2)·C B) (R1 · R2)·C C) (R1 – R2)·C D) √(R1 · R2)·C Answer: A Explanation: f = 1.44 / ((R1 + 2R2)·C); frequency decreases as the product of resistance and capacitance increases. Question 55. In a digital system, metastability is most likely to occur when: A) Two asynchronous signals change simultaneously. B) A clock edge arrives too close to a data transition. C) The supply voltage fluctuates. D) The temperature exceeds the rated limit. Answer: B Explanation: Metastability arises when a flip-flop’s data input changes near the clock edge, violating setup/hold times. Question 56. The Nyquist theorem for sampling states that to avoid aliasing, the sampling frequency must be at least: A) Twice the highest frequency component of the signal. B) Equal to the highest frequency component. C) Half the highest frequency component. D) Ten times the highest frequency component. Answer: A Explanation: f_s ≥ 2·f_max ensures the sampled signal can be perfectly reconstructed. Question 57. In a binary weighted DAC using an R-2R ladder, the value of the most significant bit (MSB) resistor is: A) R
D) Temperature coefficient. Answer: C Explanation: β is the DC current gain, the ratio of collector current to base current. Question 61. A differential amplifier rejects common-mode signals. Its common-mode rejection ratio (CMRR) is expressed in: A) Volts B) Amperes C) Decibels (dB) D) Hertz Answer: C Explanation: CMRR is the ratio of differential gain to common-mode gain, usually given in dB. Question 62. Which of the following is true for a class-B power amplifier? A) Conducts over the full 360° of the input cycle. B) Conducts over 180° of the input cycle per transistor. C) Has zero crossover distortion. D) Operates with a single transistor only. Answer: B Explanation: Class-B uses two complementary transistors, each conducting for half the cycle (180°). Question 63. In a 4-bit ripple-carry adder, the worst-case propagation delay is proportional to: A) 1 × t_gate B) 2 × t_gate C) 4 × t_gate D) 8 × t_gate Answer: C
Explanation: Each full adder must wait for the carry from the previous stage; delay grows linearly with number of bits (4 stages). Question 64. The logical expression for a 2-input XOR gate is: A) A · B B) A + B C) A·¬B + ¬A·B D) ¬A·¬B + A·B Answer: C Explanation: XOR is true when inputs differ: A·¬B + ¬A·B. Question 65. In a synchronous serial communication, the term “baud” often equals the data rate because: A) One symbol carries one bit. B) Multiple bits are encoded per symbol. C) The line is always idle. D) Baud and bit rate are unrelated. Answer: A Explanation: For NRZ (non-return-to-zero) encoding, each symbol represents a single bit, so baud = bits per second. Question 66. The primary function of a voltage regulator (linear type) is to: A) Convert AC to DC. B) Maintain a constant output voltage despite variations in input voltage or load. C) Increase voltage level. D) Provide isolation. Answer: B Explanation: Linear regulators drop excess voltage to keep the output steady. Question 67. In a three-phase delta-connected load, the line voltage is: A) Equal to the phase voltage.
