Error, Detection Techniques - Data Communication - Lecture Slides, Slides of Data Communication Systems and Computer Networks

Error Detection Techniques, Types of Errors, Redundancy, Types of Redundancy Checks, Single Bit Error, Vertical Redundancy Check, Performance of VRC are points you can learn these slides.

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2011/2012

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Lecture-33
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DATA

COMMUNICATION

Lecture-

Recap of Lecture 32

 T-Lines in Analog Transmission

 Fractional T-Lines

 E-Lines

 Fiber To The Curb (FTTC)

 Error Detection and Correction

Types of Errors

Single-Bit Error

 Only one bit of a given data unit is changed

 The least likely type of error in serial transmission

 Single-bit error can happen in parallel transmission

Burst Error

 Two or more bits in the data unit are changed

 Most likely to happen in a serial transmission

 Number of bits affected depends on the data rate and duration of noise

Burst Error

Redundancy

Detection Methods

 Four types of redundancy checks

 VRC, LRC, and CRC: For use in the data link layer

 Checksum: Used by upper layers

Vertical Redundancy Check

 Often called a Parity Check

 A parity bit is added to every data unit

 Even-parity checking or odd-parity checking

Vertical Redundancy Check

Example 9.

 Suppose “world” is received by the receiver without being corrupted:

 Receiver counts the 1’s and passes it 1110111 w 1110111 0 6 1101111 o 1101111 0 6 1110010 r 1110010 0 4 1101100 l 1101100 0 4 1100100 d 1100100 1 4

Example 9.

 Suppose “world” is received by the receiver corrupted:

 Receiver counts the 1’s and rejects it 1110111 w 1111111 0 7 1101111 o 1101111 0 6 1110010 r 1110110 0 5 1101100 l 1101100 0 4 1100100 d 1100100 1 4

Performance of VRC

 We have an Even Parity data unit where the total number of 1’s including the parity bit is ‘6’ : 1000111011

 If 3 bits change value resulting parity will be odd and an error will be detected: 1111111011: 1’s = 9

Performance of VRC

 If 2 bits change value resulting parity will still be even and error will not be detected: 1110111011: 1’s = 8

 VRC cannot detect errors when the total number of bits changed are even