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Errata
CMOS VLSI Design 3 rd^ Edition
Last updated 4 September 2006 Send your corrections to [email protected]
Errata in 2 nd^ Printing
Page viii, Section 4.3: “SIzing” -> “Sizing” (N. Ho 8/16/06)
Page 39, Table 1.7: “PC <- PC+imm” -> “PC <- PC + 4 + imm*4” (E. Brunvand 11/7/05)
Page 41, Fig 1.52, beq: 0000000000000101 10600005 -> 0000000000000100 10600004 (E. Brunvand, 11/7/05)
Page 41, Fig 1.52, last line: encoding for sb should be 101000, not 110000 (E. Brunvand 11/7/05)
Page 67, Fig 2.1 should be:
(a) (b) (c) (D. Rancour, 8/5/05)
Page 67, Footnote: 2.4.5 -> 2.4.6 (J. Jung, 7/16/05)
Page 99, line 7: 0.34 -> 0.13 (D. Rancour 8/9/05)
Page 100, Section 2.5.4: Delete Optional (D. Rancour, 8/9/05)
Page 104, Fig 2.34: pMOS should swap “d” and “s” labels (K. Neilsen 6/1/05)
Page 144, bottom paragraph: “pitch is P = W+S” -> “pitch, in turns per meter, is P = 1/2(W+S)”
Page 190, Example line 2: 1:32 -> 5:32 (K.T. Lau, 1/26/06)
Page 199, line 1-2: “sheet resistance” -> “resistivity” (G. Venturini, 1/29/06)
Page 223, next to last paragraph, line 4: “thorough” -> “through” (G. Jedhe 9/11/05)
Page 362, paragraph 4, line 9: ‘correct output Y” -> “correct output Y ”, (D. Rancour 9/1/05)
Page 407, 3 rd^ paragraph, line 2, Figure 7.17(j) -> Figure 7.17(k) (DH 5/22/05)
Page 476, exercise 7.8. Add “Express the times relative to the rising edge of φ 1 .” (R. Lethin 10/13/05)
Page 508, Fig 8.26: one of the transistors is missing a third contact and the blue stipple Lines should be behind contacts (Y. Dong 2/25/06)
Page 701, paragraph 3, line 4: “e (^) i = M (^) i xor y 15 ” -> “e (^) i = PP (^) iN (e.g. the most significant bit of the i th partial product)” (G. Prasad 11/05)
Page 851, line 2: add space after “input” to align [ (DH 9/24/05)
Page 853, Table A1: delete comma after >> (DH 9/24/05)
Page 856, module mul: add space after “input” to align [ (DH 9/25/05)
Page 857, change two lines to delete illegal reversed range b[1:3] (DH 9/29/05) assign y = {a[2:1], {3{b[0]}, a[0], 3'b101}; y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 1
Page 900, Table B1: delete shading from “not” row (DH 9/24/05) Delete row with =, = =, !=
Page 909: delete reference to @ list (DH 9/25/05)
Page 915: Output logic should be (H. Zhu 8/7/05) -- output logic x <= '1' when ((state = s1 or state = s2) and a = '0') or ((state = s3 or state = s4) and a = '1') else '0'; y <= '1' when ( state = s2 and a ='0') or (state = s4 and a = '1') else '0';
Page 942, [Naffziger 02]: implementnation -> implementation (DH 5/3/06)
Errata in 1 st^ Printing (corrected in 2 nd^ printing, Spring 2005)
Many figures have incorrect metal2 stipple (either blank or hashed) caused by a bug in the printer software. These include: 1.39, 1.44, 1.61, 1.62, 1.67, 3.8, 3.11, 3.18, 3.20, 4.31, 4.33, 8.27, 8.28, 8.29, 8.52, 8.53, 10.5, 10.65, 11.3, 11.5, 11.6, 11.38, 11.39, 11.50, 11.58, 12.6, 12.7, 12.23, (DH 5/12/04)
Some figures have lines that don’t meet up properly caused by poor registration between blue and black by the printer. (DH 5/13/04) 3.21, 11.24, 11.25, 11.27, 11.28,
Page 110, Exercise 2.14: Before lasts sentence, add “Assume βn = βp = β and Vtn = |V (^) tp | = Vt .” (DH)
Page 115, end of 3rd paragraph. Should read "... made thinner. This in turn makes them ..." (instead of "This is turn") (J. Frenzel 2/6/05)
Page 124, paragraph 3: "Pirhana solution" -> "Piranha solution" (S. Kabadayi 10/4/04)
Page 131 - last paragraph: "Section 1.6.5" should be "Section 1.5.5." (J. Frenzel 2/6/05)
Page 137, line 2: "leakge" -> "leakage" (S. Kabadayi 10/4/04)
Page 145, paragraph 4: “ground lane” -> “ground plane” (Sproull 6/1/04)
Page 161, Eq 4.1: “j=i” -> “j=1” (Sproull 6/1/04)
Page 191, Example, line 1: “page 99” -> “page 189” (J. Frenzel 2/28/05)
Page 213, last line of example: “writ-“” -> “writing.” (Jun Shi 11/11/04)
Page 243, Fig 4.66 Missing oxide on Y between metal1 and substrate. (J. Frenzel 2/6/05)
Page 266, Exercise 4.3: “AND-OR-INVERT” -> “unloaded AND-OR-INVERT” (DH)
Page 269, Exercise 4.25: 300 pF -> 300 fF (DH 10/27/04)
Page 277, table 5.2: mili -> milli (S. Carriere, 11/25/04)
Page 282, figure 4.9: e and f line patterns should be interchanged (S. Carriere, 11/24/04)
Page 284, paragraph 2: “and four inverters.” -> “and five inverters.” (S. Carriere, 11/24/04)
Page 284, paragraph 2: “inverter is subcircuit (X)” -> “inverter is a subcircuit (X)” (S. Carriere, 11/24/04)
Page 341, paragraph 3: "p = 2.76" => "ρ = 2.76" (Sproull 6/1/04)
Page 343, 2 nd^ to last paragraph: “dynamic p-logic NOR” -> “dynamic p-logic NAND” (M. Abdeen, 2/18/05)
Page 346: DCVSPG and PPL schematics should reverse Y and Ybar (DH)
Page 372, line 3: “actually subthreshold” -> “actually have subthreshold” (Sproull 6/1/04)
Page 380, Exercise 6.24: 2 nd^ sentence: pull-up should be four times as strong as pull- down. Last sentence: compare to static CMOS 2-input NAND. (DH 6/27/04)
Page 381, Exercise 6.36: each input can drive 10 unit transistors (DH)
Page 400, fig 7.15: t_pdq should be t_pd (D. Ha 2/7/05)
Page 407, Fig 7.21: Exchange bubbles on phi2/phi2b (two places) (M. Senlik, 12/29/04)
Page 409, Fig 7.24: Asynchronously Resettable flip-flop should be redrawn as (A. Rainier 3/9/05):
D
φ
φ
φ
φ
Q
Q φ
φ
φ
φ
reset φ
φ
φ^ Q
φ
D
reset
φ
φ
Q φ
φ
D
reset
reset
Synchronous Reset
Asynchronous Reset
Symbol D^ LatchQ D^ Flop Q
reset reset
φ φ
D
φ
φ
φ
φ
φ
φ
Q φ
φ
reset
reset
Page 413, Fig 7.29: Delete funny box after text. (DH 4/04)
Page 423, Fig 7.39: 1.2, 1.4, and 1.6 labels on x axis are garbled and should be placed beneath tick marks. J. Frenzel 3/22/05.
Page 440, Figure 7. 58(a) the label for the fourth wave form: clkbddd -> clkddd (D. Ha 2/15/05)
Page 463, Fig 7.88(b): ack1 and ack2 should be swapped. J. Frenzel 4/4/05.
Page 473, Table 7.4: equation is missing from pulsed latch time borrowing: t_pw – (t_setup + t_skew) (DH)
yj yj-
PP (^) ij
Booth Selector
x2i+
x2i
x2i-
Mi
Xi
2Xi
Booth Encoder
(E. Brunvand 2/16/05)
Page 710, Exercise 10.2: Change last sentence to “… function of the most significant bits of the two inputs and the output.” (DH)
Page 710, Exercise 10.3: Change last sentence to “…function of the sub signal and the most significant bits of the two inputs and the output.” (DH)
Page 710, Figure 10.87: Delete (b) (DH)
Page 710, Exercise 10.6: Change to “The carry increment adder in Figure 10.31(b)…” (DH)
Page 723, Fig 11.14: Switch inverted and noninverted inputs A2, A1, A0. (DH)
Page 727, Figure 11.19: swap bars on A1/A1bar and A2/A2bar (R. DiGiacomo, 12/19/04)
Page 732, 3 rd^ to last line: 2 N^ should be 2 N (DH)
Page 792, Fig. 12.32: Upper left transistor in charge pump should be tied to bias voltage, not to VDD. T. Saito 1/
Page 810, EQ 12.16: r 0 should be r (^) o (DH)
Page 815, EQ (12.23): R 1 should be R DH 10/21/
Page 865, priority_if figure: the output should be y[3:0] instead of a[3:0]. A. Rainier 1/27/
Page 866, priority_assign figure: the output should be y[3:0] instead of a[3:0]. A. Rainier 1/27/
Page 866, ram figure: the input should be addr[5:0] instead of adr[5:0]. A. Rainier 1/27/
Page 873, first paragraph: “tempted so” -> “tempted to” A. Rainier, 1/27/
Page 886, mipstest assembly. “Machine Code” and 8-digit opcodes should be aligned in a column. DH 1/18/
Page 929, [Chern92]: P. Yang,” Multimetal -> P. Yang, “Multimetal (D. Suarez, 3/16/05)
Index: entries from page 136-154 are misnumbered (S. Carriere, 11/25/04) p. 138 (should be 136) Multiple threshold voltages Threshold voltage Subthreshold Gate oxide Silicon on Insulator SOI P 139 (should be 137) Sapphire Buried oxide Dielectric Subthreshold Finfet p. 140 (should be 138) mobility SiGe p. 141 (should be 139) strained silicon plastic transistors transistor; plastic p. 142 (should be 140) copper damascene process dual damascene p. 142 (should be 141) low-k dielectric fluorosilicate glass p. 143 (should be 141) SiLK Capacitor MOS capacitor
p. 150 (should be 148) carbon nanotube nanotubes p. 150 (should be 149) run set p. 151 (should be 149) Dracula Nwell Active P-select n-select poly contact metal p. 153 (should be 151) breakdown voltage p. 154 (should be 152) diode p. 155 (should be 153) resolution enhancement
