15.5. MIPS Exception Handling
MIPS exceptions are handled by a peripheral device to the CPU called coprocessor
0 (cp0). Coprocessor 0 contains a number of registers used to configure exception
handling and to report the status of current exceptions.
•The EPC register, cp0 register 14, is the exception program counter. It
contains the address of the instruction that was running when the exception
occurred. It serves the same purpose for the exception handler that CPU
register $ra serves for ordinary subprograms. When the exception handler
completes, the EPC register allows the program that was interrupted to be
resumed.
•The cause register, cp0 register 13, contains bits that identify the cause of
the exception.
•The badvaddress register, cp0 register 8, contains the address that caused a
bad address exception.
•The status register, cp0 register 12, is used both to configure interrupts, and
get more information about the exception that occurred.
MAL has no aliases for the cp0 registers, so they must be referred to as register
numbers. For example, the status register is referred to as $12.
Registers in coprocessor 0 cannot be used directly by MIPS instructions. Instead,
there are two instructions that work much like load and store instructions.
The mfc0 (move from coprocessor 0) instruction loads data from a coprocessor 0
register into a CPU register. The mtc0 likewise stores data in a cp0 register.
Note
The mtc0 instruction, like the store instruction has the destination last. This is
especially important to note, since the syntax for cp0 registers looks the same as
the syntax for CPU registers. For example, the following copies the contents of
CPU register 13 to cp0 register 12.
mtc0 $13, $12
Since cp0 registers cannot be accessed by most instructions, changing their values
requires using the read-modify-write cycle. This means we must
1. Read the cp0 register into a CPU register
2. Modify the contents of the CPU register
3. Write the modified value back to the cp0 register
The read-modify-write cycle is extremely common in interacting with I/O devices
and other system hardware.
Exceptions generated by SPIM include overflow and bad address traps, and
keyboard and display interrupts.
The SPIM single-step feature cannot be used with exception handling. If you are
accustomed to using single-stepping for debugging, try using breakpoints instead.
