Exercise Study Guide for Computer Architecture | COSC 6385, Assignments of Computer Architecture and Organization

Material Type: Assignment; Professor: Gabriel; Class: Computer Architecture; Subject: (Computer Science); University: University of Houston; Term: Fall 2008;

Typology: Assignments

Pre 2010

Uploaded on 08/19/2009

koofers-user-8nr
koofers-user-8nr 🇺🇸

10 documents

1 / 3

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
COSC 6385 Computer Architecture
Exercises
Name:_______________________________________
1. Caches
a) The average memory access time (AMAT) can be modeled using the
following formula:
AMAT = Hit time + Miss rate * Miss penalty
Name and explain (briefly) one technique for each of the three components of
the formula in order to decrease the average memory access time.
Pick one of each block:
Reducing Miss penalty:
- Multilevel caches: 1st level small, but at the speed of the CPU, 2nd level
larger but slower
- Critical word first: don’t wait until the entire cache-block has been load,
focus
- on the required data item: ask for the required data item, Forward the data
item to the processor, Fill up the rest of the cache block afterwards
- Early restart: don’t wait until the entire cache-block has been load, focus
- on the required data item: Fetch words of a cache block in normal order,
Forward the requested data item to the processor as soon as available, Fill up
the rest of the cache block afterwards
- Giving priority to read misses over writes
- Merging write buffer: Check in the write buffer whether multiple entries can
be merged to a single one
- Victim caches: fully associative cache between the ‘real’ cache and the
memory keeping blocks that have been discarded from the cache
- )onblocking caches
- Hardware prefetch of Instructions and Data
- Compiler controlled prefetching
Reducing Miss rate:
- Larger cache block size
- Larger caches
- Higher associativity
- Way prediction and pseudo-associative caches
- Compiler optimization
Reducing Hit time:
- Small and simple caches
- Avoiding address translation
- Pipelined cache access
- Trace caches
( 3 Pts)
pf3

Partial preview of the text

Download Exercise Study Guide for Computer Architecture | COSC 6385 and more Assignments Computer Architecture and Organization in PDF only on Docsity!

Exercises

Name:_______________________________________

  1. Caches a) The average memory access time (AMAT) can be modeled using the following formula:

AMAT = Hit time + Miss rate * Miss penalty

Name and explain (briefly) one technique for each of the three components of the formula in order to decrease the average memory access time.

Pick one of each block: Reducing Miss penalty:

  • Multilevel caches: 1st level small, but at the speed of the CPU, 2nd level larger but slower
  • Critical word first: don’t wait until the entire cache-block has been load, focus
  • on the required data item: ask for the required data item, Forward the data item to the processor, Fill up the rest of the cache block afterwards
  • Early restart: don’t wait until the entire cache-block has been load, focus
  • on the required data item: Fetch words of a cache block in normal order, Forward the requested data item to the processor as soon as available, Fill up the rest of the cache block afterwards
  • Giving priority to read misses over writes
  • Merging write buffer: Check in the write buffer whether multiple entries can be merged to a single one
  • Victim caches: fully associative cache between the ‘real’ cache and the memory keeping blocks that have been discarded from the cache
  • )onblocking caches
  • Hardware prefetch of Instructions and Data
  • Compiler controlled prefetching

Reducing Miss rate:

  • Larger cache block size
  • Larger caches
  • Higher associativity
  • Way prediction and pseudo-associative caches
  • Compiler optimization

Reducing Hit time:

  • Small and simple caches
  • Avoiding address translation
  • Pipelined cache access
  • Trace caches

( 3 Pts)

Exercises

Name:_______________________________________ b) Consider two identical machines differing only in the cache organization. The first machine has a 2-way set-associative cache, the second machine has a 4- way set-associative cache. The 1st^ machine has a clock cycle time of 1.25ns and a miss rate of 1.0%, while the 2nd^ machine has a clock cycle time of 1.4ns. Assuming a CPI of 2.0 for perfect cache behavior, 1.5 memory references per instruction, a cache miss penalty of 75ns, and a cache hit time of 1 clock cycle, determine the miss rate of the second machine in order for the four-way set associative cache to have a lower average memory access time than the first machine.

AMAT 1 = 1.25 + ( 0.01 * 75) = 2.0ns AMAT 2 = 1.4 + (x * 75)

AMAT 2 < AMAT 1 if 1.4 + 75x < 2. -> x < (2.0-1.4)/75 = 0.008 = 0.8%

c) In the following, we would like to determine the set associativity leading to the minimal average memory access time. The miss penalty is still 75ns. A cache hit takes one clock cycle. However, the clock cycle time is depending on the set associativity n, with n=1 being a direct mapped cache, n=2 being a 2-way set associative cache etc. The formula describing the dependence between the clock cycle time and the set associativity is:

Clock cycle time(n) = 1.0 + 0.02*n^2

Similarly, the Miss rate depends on n and can be described by the formula

Miss rate = 0.01 – 0.002*n

  1. Give the formula for the overall Average Memory Access Time (AMAT) depending on n.

AMAT(n) = 1.0 + 0.02n^2 + ( 0.01 – 0.002n) * = 1.0 + 0.02n^2 + 0.75 – 0.15n = 0.02n^2 - 0.15n + 1.

( 2 Pts)

( 1 Pts)