Pipeline Hazards and Forwarding in Systems Architecture II, Study notes of Computer Science

Pipeline hazards, forwarding, and stalls in the context of systems architecture ii. It covers topics such as data hazards, control hazards, and exceptions, as well as techniques for handling them like dynamic branch prediction and delayed branches. The document also includes timing diagrams and examples to illustrate the concepts.

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Uploaded on 08/19/2009

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Lec 3 Systems Architecture II 1
Systems Architecture I
Topics
Dealing with Pipeline Hazards*
Exploiting Memory Hierarchy: Cache Memory**
*This lecture was derived from material in the text (Chapter 6).
**This lecture was derived from material in the text (Chapter 7).
Notes Courtesy of Jeremy R. Johnson
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Lec 3

Systems Architecture II

Systems Architecture I

Topics

Dealing with Pipeline Hazards

**Exploiting Memory Hierarchy: Cache Memory****

*This lecture was derived from material in the text (Chapter 6). **This lecture was derived from material in the text (Chapter 7).

Notes Courtesy of Jeremy R. Johnson

Lec 3

Systems Architecture II

Systems Architecture II

Topic 1: Dealing with Pipeline Hazards

Lec 3

Systems Architecture II

Data Hazards and Forwarding

Problem: Instruction depends on the result of a previousinstruction still in the pipeline

Example

sub $2, $1, $

and $12, $2, $

or

$13, $6, $

add $14, $2, $

sw

$15, 100($2)

Lec 3

Systems Architecture II

Timing Diagram with Data

Dependencies

IM
Reg^ IM
Reg
CC 1
CC 2
CC 3
CC 4
CC 5
CC 6
Time (in clock cycles)
sub $2, $1, $
Programexecutionorder(in instructions)
and $12, $2, $
IM
Reg
DM
Reg
IM
DM
Reg
IM
DM
Reg
CC 7
CC 8
CC 9
  • 20
  • 20
  • 20
  • 20
or $13, $6, $2add $14, $2, $2sw $15, 100($2)
Value of register $2:
DM
Reg
Reg
Reg
DM Reg

Lec 3

Systems Architecture II

Forwarding

IM
Reg
IM
Reg
CC 1
CC 2
CC 3
CC 4
CC 5
CC 6
Time (in clock cycles)
sub $2, $1, $
Programexecution order(in instructions)
and $12, $2, $
IM
Reg
DM
Reg
IM
DM
Reg
IM
DM
Reg
CC 7
CC 8
CC 9
  • 20
  • 20
  • 20
  • 20
or $13, $6, $2add $14, $2, $2sw $15, 100($2)
Value of register $2 :
DM
Reg
Reg
Reg
Reg
X
X
X
  • 20
X
X
X
X
X
Value of EX/MEM :
X
X
X
X
  • 20
X
X
X
X
Value of MEM/WB :
DM

Lec 3

Systems Architecture II

Pipelined Datapath with Forwarding

Registers

Mux

Mux

ALU

ID/EX

MEM/WB

Data memory

Mux

Forwarding

unit

EX/MEM

b. With forwarding

ForwardB

Rd

EX/MEM.RegisterRdMEM/WB.RegisterRd

RsRtRt

ForwardA

Mux

ALU

ID/EX

MEM/WB

Data memory

EX/MEM

a. No forwarding

Registers

Mux

Lec 3

Systems Architecture II

Datapath with Control for Forwarding

PC

Instruction

memory

Registers

Mux

Mux

Control

ALU
WB^ M^ EX
WB^ M
WB
ID/EX
EX/MEM
MEM/WB

Data memory

Mux

Forwarding

unit

IF/ID

Instruction

Mux

Rd

EX/MEM.RegisterRdMEM/WB.RegisterRd

RsRtRt

IF/ID.RegisterRsIF/ID.RegisterRtIF/ID.RegisterRtIF/ID.RegisterRd

Lec 3

Systems Architecture II

Example 1

PC

Instruction

memory

Registers

Mux Mux

Mux

WB^ M^ EX
WB

Data memory

Mux

Forwarding

unit

Instruction

IF/ID

and $4, $2, $

sub $2, $1, $

ID/EX

before<1>

EX/MEM

before<2>

MEM/WB

or $4, $4, $2 Clock 3

Control

ALU
WB^ M

Lec 3

Systems Architecture II

Example 3

PC

Instruction

memory

Registers

Mux Mux

Mux

WB^ M^ EX
WB^ M

Data memory

Mux

Forwarding

unit

Instruction

IF/ID

add $9, $4, $

or $4, $4, $

ID/EX

and $4,...

EX/MEM

sub $2,...

MEM/WB

after<1> Clock 5

Control

ALU
WB

Lec 3

Systems Architecture II

Example 4

PC

Instruction

memory

Mux Mux

Mux

WB^ M^ EX
WB^ M

Data memory

Mux

Forwarding

unit

after<1>

after<2>

add $9, $4, $

or $4,...

EX/MEM

and $4,...

MEM/WB

Clock 6

ALU
WB

Registers

Instruction

IF/ID
ID/EX

Control

Lec 3

Systems Architecture II

Inserting Stalls into the Pipeline

If (ID/EX.MemRead and

((ID/EX.RegisterRt = IF/ID.RegisterRs) or

(ID/EX.RegisterRt = IF/ID.RegisterRt)))

stall the pipeline (insert nop by setting control = 0)

lw $2, 20($1)
Programexecutionorder(in instructions)
and $4, $2, $5or $8, $2, $6add $9, $4, $2slt $1, $6, $
Reg
IM
Reg
Reg^ IM
DM
CC 1
CC 2
CC 3
CC 4
CC 5
CC 6
Time (in clock cycles)
IM
Reg
DM
Reg
IM
IM
DM
Reg
IM
DM
Reg
CC 7
CC 8
CC 9
CC 10
DM
Reg
Reg
Reg
Reg

bubble

Lec 3

Systems Architecture II

Datapath with Control for Stalls

PC

Instruction

memory

Registers

Mux Mux

Mux

Control

ALU
WB^ M^ EX
WB^ M
WB
ID/EX
EX/MEM
MEM/WB

Data memory

Mux

Hazard detection

unit

Forwarding

unit

Mux

IF/ID

Instruction

ID/EX.MemRead

IF/IDWrite

iter PCW

IF/ID.RegisterRsIF/ID.RegisterRtIF/ID.RegisterRt IF/ID.RegisterRdID/EX.RegisterRt

Rt Rd RsRt

EX/MEM.RegisterRdMEM/WB.RegisterRd

Lec 3

Systems Architecture II

Example 2

Hazard detection

unit

Mux

IF/IDWrite

PCWrite

ID/EX.RegisterRt

lw $2, 20($1)

PC

Instruction

memory

Registers

Mux Mux

Mux

WB^ M^ EX
WB

Data memory

Mux

Forwarding

unit

Instruction

IF/ID

and $4, $2, $

ID/EX

before<1>

EX/MEM

before<2>

MEM/WB

or $4, $4, $2 Clock 3

$1 $X 1 X 2

Control

ALU
M
WB

ID/EX.MemRead

Lec 3

Systems Architecture II

Example 3

$2 $5^25
WB
Hazard
detection
unit
Mux
IF/IDWrite
PCWrite
ID/EX.RegisterRt
PC
Instruction
memory
Registers
Mux Mux
Mux
WB^ M^ EX
Data
memory
Mux
Instruction
IF/ID

and $4, $2, $

bubble

ID/EX

lw $2,...

EX/MEM

before<1>

MEM/WB

Clock 4

Control
ALU
WB^ M
Forwarding
unit
ID/EX.MemRead

or $4, $4, $