ECE3055 Prof. H.-H. S. Lee
Georgia Tech Page 1 of 2
ECE3055 Fall 2006
Programming Assignment 3
Hazard Control
Assigned: Nov 8, 2006 Signoff Before Nov 22, 2006
Score: ____________ Date:___________ Name:__________________________________
TA Signoff: ________________________________________________________________
Part I: Forwarding
Continuing from your pipelined MIPS design in Programming Assignment 2, data hazards could
occur between the five instructions present in the pipeline. For instance, consider the following
program:
sub $6, $5, $3
add $2, $4, $6
The subtract instruction stores a result in r6 and the following add instruction uses r6 as a
source operand. The new value of r6 is written into the register file by sub in the write-back
stage after the old value of r6 was read out by add in the decode stage.
In the text, this problem is fixed by adding two forwarding multiplexers to each ALU input in the
execute stage. In addition to the existing values feeding in the two ALU inputs, the forwarding
multiplexers can also select the last ALU result or the last value in the data memory stage. These
muxes are controlled by comparing the rd, rt, and rs register address fields of instructions in
the ID, EX, or MEM stages. Instruction rd fields will need to be added to the pipelines in the
EX, MEM, and WB stages for the forwarding compare operations. Since r0 is always zero, do
not forward r0 values. The forwarding muxes in the EX stage handle dependences on
instructions in the EX and MEM stages.
For Part II of the assignment with Branches you will need to have the ALU’s data forwarding
muxes moved back into the ID stage, so if you intend to work both parts, you might save time by
moving the forwarding muxes to the ID stage for Part I of the assignment. Note that the mux
signals to forward are now needed one clock cycle earlier, so you will need to rework the text’s
forwarding equations to reflect this change before coding them in VHDL. It would be a good idea
to work through several examples by hand to double check your new forwarding equations. If
necessary, draw a picture like Fig 6.34 to obtain the new forwarding equations. You can assume
that there is enough time in a single clock cycle to take the current ALU output (before a pipeline
register) and forward it to the ID stage for a branch decision.
Dependence from an instruction in the WB stage to one in the ID stage must also be considered.
You can handle this dependence in one of 2 ways. The first method is to ensure that the
assumption used in Patterson and Hennessy holds, i.e. that the register file write in one cycle
occurs before the register file read in the same cycle. This can be accomplished by writing to the
register file on the falling edge (instead of the rising edge) of each clock cycle. A register file
read from the same register will then have its value clocked into the ID/EX pipeline register at the
next rising edge, ensuring that the just-written value is passed to the EX stage. The second
