1
9-3.
9-6.
9-9.
9-11.
LD R1, A
LD R2, B
LD R3, C
LD R4, D
ADD R3, R1, R3
ADD R1, R1, R2
MUL R2, R2, R4
MUL R1, R3, R1
SUB R1, R1, R2
ST Y, R1
MOV T1, A
ADD T1, C
MOV T2, B
MUL T2, D
MOV T3, A
ADD T3, B
MUL T3, T1
SUB T3, T2
MOV Y, T3
LD A
ADD C
ST T1
LD B
MUL D
ST T2
LD A
ADD B
MUL T1
SUB T2
ST Y
a) b) c)
AB+()AC+()รBDร()AB CA+BD โรร+=โ
A)
PUSH A PUSH B ADD PUSH A PUSH C ADD
ABA+BA CA+C
AA+BAA+B
A+B
MUL PUSH B PUSH D MUL SUB
(A+B)x(A+C) B D BxD (A+B)x(A+C) - BxD
(A+B)x(A+C) B (A+B)x(A+C)
(A+B)x(A+C)
B,C)
a) X = 200 โ 208 โ 1 = โ9 b) X = 1111 1111 1111 0111
address field = 0
a) 3 Register Fields x 5 bits/Field = 15 bits. 32 bits - 15 bits = 17 bit. 217 = 131,072
b) 256 = 8 bits. 2 Register Fields x 5 bits/Field = 10 bits. 32 bits - 8 bits - 10 bits = 14 Memory Bits
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