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ENEE350H Fall 2003
Final Examination Pages: 10 printed sides Name: _________________________________________ Time alloted: 2 hours Student ID: ______________________________________ Maximum score: 90 points
University rules dictate strict penalties for any form of academic dishonesty. Looking sideways will be penalized to the fullest extent. Look at only your own exam at all times.
There are 10 questions, some with subparts. Read them carefully to avoid throwing away points!! Write your answer in the space provided. Closed book, closed notes. Calculators okay.
Partial credit rule: Must show your intermediate steps clearly for partial credit!
1. Fill in the blanks with at most three words: (1 point * 15 = 15 points) (a) Using a _______________________________ data structure for the symbol table of an assembler delivers O(1) lookup of symbol names.
(b) One advantage of using procedures instead of macros for repeated code sequences is lower ________________________.
(c) __________________________ variables are not allocated as part of the assembly code; instead they are allocated at runtime from a free list, and referenced through pointer variables.
(d) The ___________________________ is a piece of software that resolves symbol declarations external to files by finding them in other files and generating correct addresses.
(e) _______________________________ are a commonly used hardware-supported mechanism for ensuring race-free programs.
(f) One advantage of ____________________________ allocation of file sectors on a disk is that a file’s location is completely specified by its starting sector and size alone.
(g) A sequence of unused sectors on a disk is called a _______________________________.
(h) Files are an abstraction provided by the ______________________________ (compiler/hardware/operating system/linker) in modern computers.
(i) When segmentation and paging are combined, the number of page tables is equal to the number of ____________________________.
(j) __________________________ is the name of a technique to reduce external fragmentation in segmentation by copying segments to be next to each other, thus combining free areas into one.
(k) Protection among processes at the main memory level is usually provided by the operating system mechanism of _____________________________.
(l) If a TLB stores page table entries from multiple processes then it is indexed by both the VPN and the ____________________________.
(m) When the _____________________________ of a process does not fit in main memory, thrashing is observed.
(n) When an interrupt arrives, the task of looking up the table of interrupt handler addresses is done by ______________________________ (hardware/software).
(o) When an exceptional event occurs at the same instruction every time the program is executed it is called a ______________________________.
2. For each subpart (i) to (xii) below, circle all correct answers from among the four given - note that more than one answer may be correct! (2 points * 12 = 24 points)
(i) Register usage conventions
(a) make separate compilation of different files from the same program possible.
(b) are needed to correctly save and restore registers upon an interrupt.
(c) may decrease register availability for program variables in some cases when compared to not using register conventions.
(d) need to be known to high-level language programmers.
(ii) The first pass of the assembler
(a) stores declared macros in the macro table.
(b) expands uses of macros.
(c) computes the address of every symbol definition.
(d) computes the address of every symbol reference.
(iii) Uses of assembler directives often include
(a) declaring global variables.
(b) declaring stack variables.
(c) specifying the alignment of variables.
(d) specifying the addressing mode of certain instructions.
(viii) In paging,
(a) pages are brought into physical memory only when they are accessed.
(b) consecutive pages in the virtual address space are consecutive in physical memory.
(c) a TLB miss causes a page fault.
(d) the same virtual address can occur in different processes and refer to different physical locations.
(ix) In caller-saves,
(a) variables that may be written to in the callee are saved and restored.
(b) saving of registers occurs at the beginning of every called procedure.
(c) the number of registers saved and restored is always less than in callee saves.
(d) separate compilation can be supported.
(x) Regarding addressing modes in DLX-like RISC architectures,
(a) the immediate mode accesses constants that are part of the instruction.
(b) pc-relative addressing is often used for addressing stack variables.
(c) register indirect or indexed addressing is most commonly used for global variables.
(d) direct addressing stores the full address of the memory location accessed in the instruction.
(xi) Expanding opcodes
(a) can be used in some cases to increase the length of immediate constants.
(b) always lead to variable-length instructions.
(c) are a way of increasing the number of allowed instructions in ISAs.
(d) may not increase decoding time if different opcode fields are decoded in different pipeline stages.
(xii) Usually, single-precision floating point registers
(a) are distinguished from general-purpose registers in instruction formats only by using different instruction opcodes for floating-point instructions.
(b) take longer to access than general-purpose registers.
(c) contain unusable (wasted) bits when compared to double-precision floating-point registers.
(d) are accessed in the decode stage of a DLX pipeline.
3. Consider the following code sequence running on a 5-stage DLX pipeline: (2 points * 3 = 6 points) SW 6(R5), R LW R1, 3(R2)
(i) Is it possible for the two instructions to ever have a dependence? Is yes, under what condition?
(ii) Assume that the latency of the data cache is one cycle to complete a memory operation. Will the above code execute correctly without stalling if the data cache is implemented as a simple memory bank with no extra logic? If no, then what is the functionality of extra logic that would enable stall-free execution? (1-2 sentences)? Assume cache hits.
(iii) Same question as (ii) above, but with a two-cycle data cache latency:
5. Consider a linked list task_list of type struct task containing descriptors of to-be-done tasks: struct task{ ... struct task *next; }; struct task *task_list; struct task *my_task;
Two processes P0 and P1 running on different processors both execute the following code to process tasks one-by-one from task_list.which is shared among the processes. The my_task variable is private to each process. The intended behavior is that each task is processed by exactly one process and all tasks are eventually completed. Unfortunately the following code is wrong.
while (task_list != NULL) { \S
my_task = task_list; \S
task_list = task_list -> next; \S
process_task (my_task); \S
(2 + 2 + 5 = 9 points) (a) Describe a scenario in which execution is incorrect because the same task is processed twice.
(b) Can the same task be processed twice if P0 and P1 are executed on the same processor instead, inside a time-sharing operating system? If yes, describe a scenario.
(c) Write a correct version of the above program using up and down semaphores on a single integer sem assumed initialized to 1. The code should allow parallel execution of process_task in a two- processor environment. Use a private integer Boolean variable done, assumed initialized to 0, which is set to 1 when task_list is empty. [ Hint : Access shared variables in critical sections only!]
6. Consider a 7200RPM disk with a single surface, 32 sectors per track, and sectors of 512 bytes. What is the average rotational latency in units of time, and the peak transfer bandwidth in unit of Mbytes/sec? (4 points) 7. A program on a single-issue pipelined processor completes one instruction per cycle except when it D- cache misses or branch-mispredicts. The program’s D-cache hit rate is h_cache , and the branch- prediction success rate using a BTB is h_branch. A fraction f_mem of the instructions are load/store instructions and a fraction f_branch are control-transfer instructions. When the D-cache misses, an extra L2 cycles are needed to access the data beyond the hit time. A correct branch prediction causes no stalls but a misprediction results in a 2-cycle stall. If the program has I instructions, how many cycles does it take to execute? (5 points)
9. A single-issue 5-stage pipelined DLX processor executes the following code fragment:
MULT Ra, Rb, Rc ADD Rd, Re, Rf
The multiply execution unit takes 4 cycles to execute while the add unit takes 1 cycle. Your friend proposes that instead of waiting for the MULT to finish, the ADD can be executed while the MULT is still executing, and then we allow the ADD to finish ahead of the MULT in the pipeline. Write the condition under which this is legal. [ Caution : consider all kinds of dependencies.] (3 points)
10. A computer has 16 pages of virtual address space but only four physical pages. Initially the physical memory is empty. A program references the virtual pages in the order 0, 2, 4, 5, 2, 4, 3, 11, 2, 10. Which references cause a page fault with the LRU page replacement policy? Show your intermediate working in the table below with three columns. Use as many rows as page faults. [To specify your final answer, in the VPN list at the bottom, circle the VPNs that cause page faults.] (5 points)
Page fault at: Evict: New contents: (VPN) (VPN) (VPNs in any order)
Answer: (Circle VPNs causing page fault): 0, 2, 4, 5, 2, 4, 3, 11, 2, 10.
