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Solution of ECE65 Final (Winter 2006)
Notes: 1. For each problem, 20% of points is for the “correct” final answer.
- Messy, incoherent papers lose point! Explain what you are doing!
- Use the following information in solving or designing circuits: OpAmps have a unity-gain bandwidth of 10^6 Hz, a maximum output current limit of 100 mA, and a slew rate of 1 V/μs. OpAmps are powered by ±15 V power supplies (power supplies not shown), NPN Si transistors have β = 200, βmin = 100, rπ = 3 kΩ, and ro = 100 kΩ. NMOS transistors have K = 0.25 mA/V^2 and Vt = 2 V. In circuit design, use 5% tolarence commercial resistor and capacitor values of 1, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2, 2.2, 2.4, 2.7, 3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 (× 10 n where n is an integer). You can also use 5 mH inductors.
Problem 1. In the circuit below, find vo in terms of v 1 and v 2 (Assume OpAmps are ideal). (10 pts)
V 2
V 1
R 2
R 1
R 3 Vo
V 1
V 2
VA
VB
_
−
−
Both OpAmps have negative feedback, so vp 1 = vn 1 = v 1 and vp 2 = vn 2 = v 2. Then, by node-voltage method:
v 1 − v 2 R 2
v 1 − vA R 1 = 0 → vA = v 1
( 1 +
R 1
R 2
) − v 2
R 1
R 2
v 2 − v 1 R 2
v 2 − vB R 3 = 0 → vB = −v 1
R 3
R 2
( 1 +
R 3
R 2
)
Then:
vo = vA − vB = v 1
( 1 +
R 1
R 2
R 3
R 2
) − v 2
( 1 +
R 1
R 2
R 3
R 2
)
vo = (v 1 − v 2 )
( 1 +
R 1 + R 3
R 2
)
Problem 2. An OpAmp circuit containing only one OpAmp is attached to a 500 Ω load. (A) Design the OpAmp circuit such that if an input voltage of Vi sin(ωt) is applied to the circuit, the output voltage would be 4Vi sin(ωt) for a frequency range of DC to 100 kHz (Assume OpAmp is ideal for this part ONLY). (B) An input voltage of Vi cos(10^5 t) is applied to the circuit. What is the maximum value of Vi for the circuit to operate per its design specifications of part A. (10 pt)
Vo
Vi
RL R 1
R 2
−
Part A: First, we find the transfer function of the circuit:
H = vo vi
Since H is independent of frequency, this circuit is an am- plifier. Because there is no phase shift between input and output, it should be a non-inverting amplifier. Prototype of the circuit is shown with
A = 1 +
R 2
R 1
Setting A = 4 and choosing R 1 = 10 kΩ, we find R 2 = 30 kΩ (both commercial values).
Part B: We need to check OpAmp limitations to find maximum Vi. Frequency response limit does not apply.
- Voltage supply limit (Saturation):
v− s ≤ vo ≤ v+ s → |Vo| ≤ 15 → AVi ≤ 15 → Vi ≤ 3 .75 V
- Slew Rate:
dvo dt = AVimω ≤ S 0 → 4 × Vi × 105 ≤ 106 → Vi ≤ 2 .5 V
- Maximum Current Limit: Ignoring the current flowing into R 2 as it is much larger than RL = 500 Ω, we find
Isc ≤ 100 × 10 −^3 → Vo = RLIsc ≤ 500 × 0. 1 → Vo =≤ 50 V
Vi = Vo A
→ Vi ≤ 12 .5 V
The slew rate limit is the most restrictive with Vi ≤ 2 .5 V.
First, let’s examine the state of transistors for different values of v 1 or v 2. If v 1 = 0.2 V, assume Q1 is in cut-off, iB 1 = 0 and vBE 1 < vγ = 0.7 V:
BE1-KVL: 0 .2 = 10^4 × 0 + vBE 1 → vBE 1 = 0.2 V < vγ
So, Q1 will be in cut-off (this is independent of state of Q2) with iC 1 = 0. Similarly, if v 2 = 0.2 V, Q2 will be in cut-off with iC 2 = 0 (this is also independent of state of Q1)
If v 1 = 5 V, assume Q1 is ON (either active or saturation), vBE 1 = vγ = 0.7 V and iB 1 > 0:
BE1-KVL: 5 = 10^4 × iB 1 + 0. 7 → iB 1 = 0.43 mA > 0
So, Q1 will be ON (this is independent of state of Q2) with iB 1 = 0.43 mA. Similarly, if v 2 = 5 V, Q2 will be ON with iB 2 = 0.43 mA (this is also independent of state of Q1).
Case 1: v 1 = v 2 = 0.2 V From above, both BJTs will be in cut-off and iC 1 = iC 2 = 0. From KCL above i = iC 1 +iC 2 = 0 and from CE-KVL above vo = 5 V. So when both inputs are “LOW”, the output is “HIGH.”
Case 2: v 1 = 0.2 V and v 2 = 5 V From above, Q1 will be in cut-off with iC 1 = 0 and Q2 will be ON with iB 2 = 0.43 mA. Assume Q2 is in saturation: vCE 2 = 0.2 and iC 2 /iB 2 < β. From CE-KVL, vo = vCE 1 = vCE 2 = 0.2 V and i = iC 2 = 4.8 mA. Since iC 2 /iB 2 = 4. 8 / 0 .43 = 11. 2 < β = 200, the assumption of Q2 being in saturation is correct and vo = 0.2 V. Therefore, when v 1 is LOW and v 2 is HIGH, the output will be “LOW.”
Case 3: v 1 = 5 V and v 2 = 0.2 V Because of the symmetry, this is similar to case 2 with Q1 and Q2 switched. Therefore, Q2 will be in cut-off with iC 2 = 0 and Q1 will be in saturation with iB 1 = 0.43 mA, vo = vCE 1 = 0.2 V and i = iC 1 = 4.8 mA. Therefore, when v 1 is HIGH and v 2 is LOW, the output will be “LOW.”
Case 4: v 1 = 5 V and v 2 = 5 V From above, both BJTs will be ON with iB 1 = iB 2 = 0.43 mA. Since BJTs have the same iB and the same vCE , both will be in the same state and iC 1 = iC 2 and i = 2iC 1 = 2iC 2. Assume both BJTs are in saturation: vo = vCE 1 = vCE 2 = 0.2 V and iC 1 /iB 1 = iC 2 /iB 2 < β. Then from CE-KVL, i = 4.8 mA and iC 1 = iC 2 = 2.4 mA. Since iC 1 /iB 1 = iC 2 /iB 2 = 2. 4 / 0 .43 =
- 6 < β = 200, the assumption of Q1 and Q2 being in saturation is correct and vo = 0.2 V. Therefore, when v 1 is HIGH and v 2 is HIGH, the output will be “LOW.”
In summary, the output is HIGH only if both inputs are LOW. Thus, this is a NOR gate.
Problem 5. Find the Q-point parameters of the FET in the circuit below. (10 pts)
0.47μF i
1 kΩ
G^ o S 100 kΩ
270 kΩ
20 V
I (^) D
I (^) D
V (^) V V V
Since we are interested in bias point of the circuit, the capac- itor is open circuit. We can replace 100 kΩ, 270 kΩ and the 20 V power supply with their Thevenin equivalent (similar to BJT bias circuits). Alternatively, since IG = 0, we can find VG by using the voltage divider formula:
VG =
100 × 103
100 × 103 + 270 × 103
× 20 = 5.41 V
Since IG = 0, the current in the 1 kΩ resistor is ID, and VS = 10^3 ID:
VGS = VG − VS = 5. 41 − 103 ID
We assume that FET is in active region: ID = K(VGS −Vt)^2 and VGS > Vt and VDS > VGS −Vt. First, substituting for ID in the above equation we get:
VGS = 5. 41 − 103 × 0. 25 × 10 −^3 (VGS − 2)^2 = 5. 41 − 0. 25 V GS^2 + VGS − 1
0. 25 V GS^2 − 4 .41 = 0
The above equation has two roots and for each case, the corresponding value of ID can be found from VGS = 5. 36 − 103 ID
VGS = 4.2 V → VS = 1.21 V and ID = 1.21 mA VGS = − 4 .2 V → VS = 9.61 V and ID = 9.61 mA
The second root is not a physical solution because if VGS = − 4. 2 < Vt = 2 V, FET should be in cut-off and ID = 0 and not 9.61 mA. Therefore, VGS = 4.2 V, VS = 1.21 V, and ID = 1.21 mA. Writing DS-KVL for FET
20 = VDS + 10^3 ID → VDS = 20 − 103 × 1. 21 × 10 −^3 = 18.79 V
(or alternatively, VDS = 20 − VS = 18.79 V). Since VGS = 4. 2 > Vt = 2 V and VDS = 18. 79 > VGS − Vt = 4. 2 − 2 = 2.2 V, our assumption of FET in active is correct.
Therefore, the bias point values are: VGS = 4.2 V, ID = 1.21 mA, and VDS = 18.79 V.
Problem 7. In the circuit below, find vo for vi ranging from −5 to +5 V. (10 pts)
i (^) o
iD i 1 io
1 kΩ v (^) 1 kΩ v −
−
Case 1: Assume diode is ON: vD = vγ = 0.7 V and iD > 0.
KVL: vo = vi − 0. 7
To check the region of validity of our assumption we need to calculate iD:
i 1 = vD 103 = 0. 7 × 10 −^3 A = 0.7 mA
io = vo 103 = 10−^3 × (vi − 0 .7)
iD = io − i 1 > 0 → io > i 1 → 10 −^3 × (vi − 0 .7) > 0. 7 × 10 −^3 → vi > 1 .4 V
So, if vi > 1 .4 V, the diode will be ON and vo = vi − 0 .7 V
Case 2: Assume diode is OFF: iD = 0 and vD < vγ = 0.7 V.
KCL: io = i 1 + iD = i 1 KVL: vi = 10^3 i 1 + 10^3 io = 2 × 103 io → io = i 1 = 0. 5 × 10 −^3 vi vo = 10^3 io = 0. 5 vi
To check the region of validity of our assumption we need to calculate vD:
vD = vi − vo = vi − 0. 5 vi = 0. 5 vi vD < vγ = 0.7 V → 0. 5 vi < 0. 7 → vi < 1 .4 V
So, if vi < 1 .4 V, the diode will be OFF and vo = 0. 5 vi.
In summary, for vi < 1 .4 V, vo = 0. 5 vi and for vi > 1 .4 V, vo = vi − 0 .7 V.
