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Information about two exam questions related to pipelining using booth's multipliers and vhdl code design. The first question asks to calculate the average number of clock cycles required to complete a computation using pipelined booth multipliers. The second question involves identifying correctness issues and fixing them in a vhdl code for a module named 'something'. The third question deals with simulating the behavior of a vhdl code for a module named 'foo'.
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Final Exam: Tue, Dec. 9, Time: 1-3 pm Exam Format: Open Book and Notes, Total Points: 150
Important Note : (1) Write your name on the top of this question sheet and submit along with your answer book (2) You need to show all your work clearly in deriving the answers. Just writing down the final answers is not enough.
Suggestion : Begin by reading all questions and do those first that you think you know best.
begin
endfor
be pipelined using two Booth’s multipliers, with each multiplier being a stage in the pipeline. Each Booth’s multiplier hardware is composed of a datapath and a controlling FSM of the type you de- signed in your lab problem. The Booth’s multiplier along with the FSM is enclosed in the box labeled “Booth’s multiplier” shown in the figure below.
ld_z FSM 2
Stage 2
External
Stage 1
External
(Booth’s multiplier) (Booth’s multiplier)
dataready
start Booth_done ld_x
ld_c ld_b
ld_a
start (^) Booth_done dataready ready1 ready
To another
register
data in Z
"consumes"
module that
To anoher
other control signals other control signals
module that A, B registers
loads data in
Since the number of clock cycles taken by a Booth multiplier to complete a multiplication is not pre- determined, each stage can take a variable # of ccs to complete. Thus an external FSM is needed for each stage in order to synchronize data transfer correctly between the stages, as shown in the above figure.
external module. Each bit inputs are asserted (made = ’1’) for exactly 5 ns by the corresponding
Thus note in particular that start1 and start2 may or may not become ’1’ simultaneously, and in the case that are not ’1’ simultaneously, it is not known in which order they will become ’1’.
output signal is asserted by module “something” (see below).
both input bit signals start1, start2 have become ’1’ in the current iteration. At the same time
The following is the VHDL behavioral description of module “something”. entity something is port (start1, start2 :in bit; x, y: in integer; z: out real; done: out bit := 0); end entity something; architecture behav of something is signal temp1, temp2: real; begin do work: process is begin wait until (start1 = ’1’); wait until (start2 = ’1’);
wait for 50 ns;
end process do work; end architecture behav;
(a) Ignoring syntax errors , if any (no synatx error has been deliberately inserted, though inadver- tently some might have crept in), in the above code, what are correctness/design problem(s) in the code (i.e., problem(s) that will cause it to function incorrectly)? Enumerate each problem clearly and explain what incorrect functioning it causes. 20
(b) Rewrite the code so that the correctness/design problem(s) are fixed. Comment the code clearly to explain the fixes. 40
Give the simulation times in the table provided on the last page. 20
that at the positive edge of every subsequent cc i.e., starting with the second cc , each of these input
Table for solution to part (a):
Table for solution to part (c):
