Finite State Machine (FSM) Design: Mealy and Moore Machines - Prof. Shantanu S. Dutt, Study notes of Digital Systems Design

Information on finite state machines (fsms), focusing on mealy and moore machines. Fsms have external inputs and state transitions depend on these inputs and the current state. How to determine states of an fsm, the difference between mealy and moore machines, and examples of their implementation. It also covers interacting fsms.

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2011/2012

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EECS 465: Digital Systems
Lecture Notes # 8
Sequential Circuit (Finite-State Machine) Design
SHANTANU DUTT
Department of Electrical and Computer Engineering
University of Illinois, Chicago
Phone: (312) 355-1314: e-mail: [email protected]
URL: http://www.eecs.uic.edu/~dutt
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Download Finite State Machine (FSM) Design: Mealy and Moore Machines - Prof. Shantanu S. Dutt and more Study notes Digital Systems Design in PDF only on Docsity!

1

EECS 465: Digital Systems

Lecture Notes # 8

Sequential Circuit (Finite-State Machine) Design

SHANTANU DUTT

Department of Electrical and Computer Engineering

University of Illinois, Chicago

Phone: (312) 355-1314: e-mail: [email protected]

URL: http://www.eecs.uic.edu/~dutt

2

Finite State Machine (FSM) Design

- FSMs are different from counters in the sense that they have external I/Ps,

and state transitions are dependent on these I/Ps and the current state.

- Example : Problem Statement

There is a bit-serial I/P line. Design an FSM that outputs a ‘0’

if an even # of 1’s have been received on the I/P line and the

outputs a ‘1’ otherwise.

  • (^) When do we need an FSM (i.e., seq ckt) to solve a problem rather than a

combinational ckt?

  • (^) Ans: When the problem requires the design to remember something about

past inputs in order to solve the problem

Note : If a +ve edge triggerred synchronous sequential circuit is being designed,

the counting of the # of 1s (i.e., the sampling of the

input(s), for a general FSM) occurs T log

+T

ff

+T

su

time

before every +ve edge.

FSM

x O/p y

CLK

CLK

x

# of

1s

even

odd

even

odd

odd

Tlog

+Tff

+T su

T log

= comb. logic delay

T ff

= FF delay

Tsu = FF setup time

4

Determining a Reset State:

  • (^) A reset state is a state the the FSM (seq ckt) should be in when it is just powered on.
  • (^) In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps
  • (^) Based on the above definition, decide if any of the states determined so far can be a

reset state. E.g., in the parity detector problem, the even state qualifies to be the reset

state, as in the reset state no i/ps recvdzero 1’s recvdeven # of 1’s recvdit can

be the even state

  • (^) If not, then need to have a separate reset state, and have the correct transitions from

this state to the other states (depending on the problem solved by the FSM).

Solution 1: (Mealy)

Even

Odd

0/

Reset

Even

Reset

[0]

Odd

[1]

Output

Input

Output

Input

Transition

Arc

Output is

dependent only

on current state

O/P is dependent

on current state and

input in Mealy

Solution 2: (Moore)

Mealy Machine: Output is associated

with the state transition, and appears

before the state transition is completed

(by the next clock pulse).

Moore Machine: Output is associated

with the state and hence appears

after the state transition take place.

5

FFs

External I/Ps External O/Ps

m 1

m 2

n n

Comb.

Logic

CLK

FFs

n

CLK

n

Output

Logic

m 2

Next State

Comb.

Logic

m 1

External

I/Ps

External Outputs

Mealy Machine Model

Moore Machine Model

even

odd

Time t : Even I/P  = propagation delay of logic of Mealy M/C

t

t+ t+T CLK

t+T CLK

+ 2

Even

x=

O/P=

O/P=

(Mealy)

Odd O/P=

(Moore)

 2

= propagation delay of O/P

logic unit of Moore M/C

7

State=

Even

State=

Odd

Reset 0

State=

Even

Reset

[0]

State=

Odd

[1]

x

FF

N.S.

Logic

CLK

Q

Q D

D-

Mealy

Moore

Assume single bit state information stored in a D-FF

CLK

x

D

Q

(state)

y 2

(Mealy O/P)

y 1

Moore O/P)

State Transition

is occurring

State Transition

is occurring

S.T. is complete.

S.T. is complete.

odd^ odd

even even even odd

0/

8

Moore M/C Implementation

D Q

R Q CLK

y 1

x=

A

0

a) D-FF

T Q

R Q

A y 2

x

CLK

b) T-FF

Moore O/P is synchronized with clock.

Mealy M/C Implementation

D Q

R Q CLK

y 2

x=

A

0 1 T Q

R Q

x

CLK

y 1

a) D-FF

b) T-FF

Mealy O/P is not synchronized with clock.

Reset

Reset

Reset

Reset

D

A

= Ax ; T A

= x

y 1

= A for Moore; y 2

= Ax for Mealy

10

Another example: A simple vending machine

Here is how the control is supposed to work. The vending machine delivers

a package of gum after it has received 15 cents in coins. The machine has a single

coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor

indicates to the control whether a dime or a nickel has been inserted into the coin slot.

The controller’s output causes a single package of gum to be released down a chute

to the customer.

One further specification: We will design our machine so it does not give

change. A customer who pays with two dimes is out 5 cents!

Vending

Machine

FSM

CLK

Reset

Coin

Sensor

Gum

Release

Mechanism

Open

Vending Machine block diagram

0C 5 C 10C 15C

States:

11

— The figure below show the Moore and Mealy machine state transition diagrams.

0 cent

[0]

5 cent

[0]

10 cent

[0]

=15 cent

[1]

Moore machine

=15 cent

10 cent

5 cent

0 cent

Mealy machine

Moore and Mealy machine state diagrams for the vending machine FSM

Reset / 0 ( N

( ND

Reset

Reset

Reset / 0

N / 0

D / 0

N / 0

N+D/

N+D

N

D

N

D

D/

N (^) D

N (^) D / 0

N (^) D

N (^) D / 0

Reset)/^

D Reset)/

Reset Reset / 1

13

Implementation using D-FFs

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

0 0 1 1

0 1 1 1

x x x x

1 1 1 1

0 1 1 0

1 0 1 1

x x x x

0 1 1 1

0 0 1 0

0 0 1 0

x x x x

0 0 1 0

K-map for D 1

K-map for D 0

K-map for Open (Moore)

D 1

= Q 1

  • D + Q 0

·N

DNQQNQNQD 0 0 0 1 1

OPEN = Q 1

·Q 0

OPEN = Q1·Q 0

  • D·Q 0

  • D·Q 1

  • N·Q 1

Moore

Mealy

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

0 0 1 0

0 0 1 1

x x x x

0 1 1 1

K-map for Open (Mealy)

14

D Q

R Q

D Q

R Q

Q 0

N

N

Q 0

Q 1

N

Q 1

D

D 0

D 1

Q 1

OPEN

D

0

Q

N

CLK

CLK

Vending machine FSM implementation based on D flip-flops(Moore).

0

Q

1

Q

Q 1

Q 0

Similarly,

a Mealy

implementation;

only the OPEN

function changes.

Reset

Reset

16

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

00 01 11 10

00

01

11

10

Q 1

Q 0

DN

0 0 x x

0 1 x x

x x x x

1 1 x x

x x 0 0

x x 0 0

x x x x

x x 0 0

0 x x 0

1 x x 1

x x x x

0 x x 1

x 0 0 x

x 1 0 x

x x x x

x 0 0 x

K-map for J (^1) K-map for K 1

K-map for J 0

K-map for K 0

K-maps for J-K flip-flop implementation of vending machine.

J

1

= D + Q

0

·N K

1

J  Q  N  Q  D

0 0 1

KQN 0 1

17

J Q

R Q

Q 1

CLK

K

J Q

R Q

Q 0

CLK

K

OPEN N

Q 0

D

N

D

Q 1

N

0

Q

1

Q

0

Q

1

Q

J-K flip-flop implementation for the vending machine example (Moore).

Similarly, a Mealy implementation; only the OPEN function changes.

Reset

19

FSM Word Problem 1:

  • Design a system that outputs a ‘1’ whenever it receives a multiple

of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x.

— Relevant information classes needed to solve the problem:

(A) A multiple of 3 # is received.

(B) A non-multiple of 3 # is received.

Questions to consider:

(1) How do we go from (A)(B)

Ans.: If a ‘1’ is received

(2) How do we go from (B)(A)

Ans.: Not clear. Need to split up (B) further into

(B1): 3y+1 # of 1’s received.

(B2): 3y+2 # of 1’s received.

Where y is an integer  0.

20

Note: (A): is 3y+0 = 3y # of 1’s received.

  • Now the transitions between the3 classes of information is clear:

(A)  (B1)  (B2)  (A)

1 received 1 received 1 received

  • Hence these classes of information can be considered states of

the required as states of the required FSM:

These 3 states can be represented by 3y+I, i = 0,1,

i=

i=

i=2 i=

[0]

i=

[0]

i=

[1]

Reset

Reset

0/

0/

0/

1/

1/

00

10

01 1

1

1

0

0

0

Mealy Machine Moore Machine

Input

Output

1/