Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
A final examination for the ece412 course offered in fall 2002. It includes instructions for the exam, five sample questions covering topics such as vliw architectural concepts, instruction encoding, speculation in epic models, predicated execution, and vector processing. Students are required to submit their answers via email.
Typology: Exams
1 / 5
This page cannot be seen from the preview
Don't miss anything!
Thursday December 19, 2002 1:30 - 4:30pm
Name: CampusID:
Question 1 This question tests your understanding of VLIW architectural concepts. a. (3pts) In a wide word, one can freely switch the position of instructions as long as the resource constraints allow such reordering. b. (3 pts) In an “Equal” latency model, one can continue to use the old contents of the destination register of an operation between the time it is issued and the time exposed latency has expired. c. (3 pts) A “Less-Than-Or-Equal-To” latency machine can be used as a “Equal” machine by reusing an operation’s destination register in the operation’s latency shadows. d. (3 pts) In trace scheduling, one can always compensate for code movement across a join point, or side entrance, with compensation code. Question 2 This question tests your understanding of instruction encoding in VLIW and EPIC models. a. (3 pts) In ”A VLIW Architecture for a Trace Scheduling Compiler” (Colwell, Nix, O’Donnel, Papworth, Rodman 1987), The ”no-op” fields of an instruction are not represented in main memory. (Contributor: Esther Resendiz) b. (3 pts) In IA-64, since operations in the same bundle are free of dependence with respect to each other, operations in the same bundle will always be issued in the same cycle. (Contributor: Victor Ma) c. (3 pts) IA-64 uses 5 bits for a template specifier to completely encode all instances of no-op instructions within a bundle. (Contributor: Amit Patel) d. (3 pts) The Tinker encoding scheme by Conte et al. allows the size of a code sequence to be independent of the compiler’s ability to schedule instructions to keep the processor resources busy. Question 3 This question tests your understanding of speculation in EPIC models. a. (3 pts) In ”Sentinel Scheduling: a Model for ...” by Mahlke et al., multiple exceptions in the same basic block are guaranteed to be detected in proper order according to the original code sequence. This is because the multiple instructions in a basic block would share a sentinel, and so the first sentinel executed will signal the first exception. b. (3 pts) In ”Sentinel Scheduling: A Model for ...” by Mahlke et al., restartable intervals may contain instructions such as calls to system I/O routines. (Contributor: Galen Rasche) c. (3 pts) In ”Three Architectural Models for Compiler-Controlled Speculative Execution” by Chang et al., page fault handling is delayed until the branch commits. (Contributor: Esther Resendiz) d. (3 pts) In IA-64, all entries of ALAT are empty when a process returns from context switch.
Question 6 This question tests your understanding of parallel processing models a. (3 pts) According to Hennessy and Patterson, “Coherence defines the behavior of reads and writes to the same memory location, while (memory) consistency defines the behavior of reads and writes with respect to accesses to other memory locations.” (Contributor: Chee Wai Lee) b. (3 pts) In a distributed memory message passing machine, the programmers can assume that a single-uniform address space is spread across processors and thus all data can be used unformly by all processors. (Contributor: Ritu Gupta) c. (3 pts) If a lock is free most of the time, a test-and-test-and-set lock should be used. On the other hand, if a lock would usually be in use when a processor tries to acquire it, a test-and-set lock should be used. (Contributor: Anand Shukla) d. (3 pts) A fetch-and-add primitive is more efficient than a test-and-set primitive when used to implement a barrier synchronization scheme. Question 7 This question tests your understanding of cache coherence protocols. a. (3 pts) In a Directory-Based Cache coherence protocol, a directory entry must keep track of (1) the state of each cache block. eg (shared, uncached, exclusive) and (2) processors that have copies of the block when it is shared. (Contributor: Yury Perzov) b. (3 pts) On multiprocessors with multilevel caches, coherence between caches of differing block sizes is a problem. Hennessy and Patterson, in Ch. 6, note that most multiprocessors solve this problem by probing the higher cache levels after a lower level cache word replacement, and invalidating that word in the higher level caches. (Contributor: Jeff Stine) c. (4 pts) In Illinois protocol, the memory block in shared state will become exclusive in one cache when after all other processors replace the block out of their caches. d. (3 pts) Any cache coherence protocol that can be implemented in a shared-bus snooping system can also be implemented in a directory-based system. Question 8 This question tests your understanding of memory consistency models. a. (3 pts) A weaker memory consistency model (like Release Consistency) can be used to emulate a stronger consistency model (like Sequential Consistency). (Contributor: Justin Quek) b. (4 pts) A Sequential Consistency model allows reads to pass writes held in reorder buffers in an out-of-order execution processor. c. (3 pts) Partial Store Ordering allows write buffers that combine some of the writes to consecutive locations even though there are reads between them. d. (3 pts) Reads are allowed to pass a Sr in the Release Consistency model.
Question 9 This question is for you to summarize your contribution to the classroom discussions or to make a contribution to the quality of future offering of the course. Summarize the contribution you have made to the classroom discussion. Give dates of your con- tribution and nature of your comments/questions, suggestions, supplementary material, services, etc. Send the answer in a SEPARATE e-mail to [email protected] with a Subject line “ECE412: Summary of Contribution.” This accounts for 10% of your final grade.
