ECE 412 Exam 2 Study Questions
Fall 2003
1. The first version of the ECE412 course simulator issued instructions in order and
had no store buffer. When the course staff first got out-of-order issue working
c.p.i. increased, rather than decreased. Then we implemented the store buffer and
c.p.i. improved substantially. Explain.
2. There are two very strong reasons why the register renaming process gets worse
as the width of the machine is increased. State both.
3. Is loop unrolling likely to have a positive or negative effect on correlated branch
predictors?
4. What is the dynamic scheduling analog of the EPIC concept of control
speculation?
5. What is the dynamic scheduling analog of the EPIC concept of data dependence
speculation?
6. Consider the following C code running on two processors of a cache coherent
shared memory multiprocessor:
Processor A: Processor B:
for (i=0; i < 5; i++) for (j=0; j < 5; j++)
x++; x++;
a. Assume x is initialized to 0. What are the possible values x can take after
both processors are done?
b. If the multiprocessor uses the Illinois protocol for cache coherence what is the
minimum and maximum number of cache invalidations that occur when the
code is run.
