Finite State Machines Lab Notes for 6.004 Spring 2009, Slides of Computer Fundamentals

These lab notes from the 6.004 finite state machines (fsm) course at mit, spring 2009, cover various topics related to fsms, including combinational logic, timing assumptions, designing a digital binary combination lock, and state transition diagrams. The notes also discuss moore and mealy machines, rom implementation, and dealing with corners in mazes.

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L06 – FSMs 1
6.004 – Spring 2009 2/24/09
(Synchronous)
Finite State Machines
Lab 2 is due Thursday
Great - Theory!
Finally!
Some ENGINEERING!
modified 2/23/09 09:27 L06 – FSMs 2
6.004 – Spring 2009 2/24/09
Our New Machine
Combinational
Logic
Current
State
New
State
Input Output
Clock
State
Registers
kk
mn
ā€¢ī˜‚Acyclic graph
ā€¢ī˜‚Obeys static discipline
ā€¢ī˜‚Can be exhaustively enumerated by a
truth table of 2k+m rows and k+n output
columns
ā€¢ī˜‚Engineered cycles
ā€¢ī˜‚Works only if dynamic
discipline obeyed
ā€¢ī˜‚Remembers k bits for a total
of 2k unique combinations
L06 – FSMs 3
6.004 – Spring 2009 2/24/09
Must Respect Timing Assumptions!
Questions:
ā€¢ī˜‚Constraints on TCD for the logic?
ā€¢ī˜‚Minimum clock period?
ā€¢ī˜‚Setup, Hold times for Inputs?
Combinational
Logic
Current
State
New
State
Input Output
Clock tCD,L = ?
tPD,L = 5ns
tCD,R = 1ns
tPD,R = 3ns
tS,R = 2ns
tH,R = 2ns
tCD,L > 1 ns
tS = tPD,L + tS,R = 7 nS
tH = tH,R- tCD,L= 1 nS
We know how fast it goes… But what can it do?
tCD,R (1 ns) + tCD,L(?) > tH,R(2 ns)
tCLK > tPD,R+tPD,L+ tS,R > 10nS
L06 – FSMs 4
6.004 – Spring 2009 2/24/09
A simple sequential circuit…
Lets make a digital binary Combination Lock:
Specification:
ā€¢ī˜‚One input ( ā€œ0ā€ or ā€œ1ā€)
ā€¢ī˜‚One output (ā€œUnlockā€ signal)
ā€¢ī˜‚UNLOCK is 1 if and only if:
Last 4 inputs were the
ā€œcombinationā€: 0110
How many
registers do
I need?
Lock
IN U
CLK
pf3
pf4
pf5

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L06 – FSMs 1

(Synchronous) 2/24/

Finite State Machines Lab 2 is due Thursday

Great - Theory! Finally!Some ENGINEERING!

modified 2/23/09 09:^

6.004 – Spring 2009^

2/24/ Our New Machine

CurrentCombinationalStateLogic

NewState

Input^

Output

StateRegistersClock

k^

k

m^

n

  • ^ Acyclic graph • ^ Obeys static discipline • ^ Can be exhaustively enumerated by atruth table of 2

k+m^ rows and k+n output

columns

  • Engineered cycles • Works only if dynamicdiscipline obeyed • Remembers k bits for a totalk^ of 2unique combinations L06 – FSMs 3

2/24/ Must Respect Timing Assumptions!Questions:^ • ^ Constraints on T

for the logic?CD

  • ^ Minimum clock period? • ^ Setup, Hold times for Inputs?

CurrentCombinationalStateLogic

NewState

Input^

Output

Clock^

t= ?CD,L^ t = 5nsPD,L^ t= 1nsCD,R^ t= 3nsPD,R^ t^ = 2nsS,R^ t^ = 2nsH,R^

t> 1 nsCD,L^ t= t^ + t^ S^ PD,L^ S,R

= 7 nS (^) t= t - t = 1 nSH H,R CD,L

We know how fast it goes… But what can it do?

t(1 ns) + t^ CD,R^ CD,L

(?) > t(2 ns)H,R^ t^ > t^ +t^ CLK^ PD,RPD,L

  • t> 10nSS,R^

6.004 – Spring 2009^

2/24/ A simple sequential circuit…Lets make a digital binary

Combination Lock: Specification: •  One input ( ā€œ0ā€ or ā€œ1ā€) •  One output (ā€œUnlockā€ signal) •  UNLOCK is 1 if and only if:Last 4 inputs were theā€œcombinationā€: 0110

IN^ Lock How manyregisters doI need?

U CLK

L06 – FSMs 5

2/24/ Abstraction

du jour: Finite State Machines •  A FINITE STATE MACHINE has m^ ClockedFSM

n

  • ^ k STATES: S

… S(one is ā€œinitialā€ state) 1 k^

  • ^ m INPUTS: I

… I 1 m

  • ^ n OUTPUTS: O

… O 1 n

  • ^ Transition Rules s’(s, I) for each state s and input I • ^ Output Rules Out(s) for each state s

6.004 – Spring 2009^

2/24/ State Transition DiagramSXS0 (^0) U=0U=

S01 1 U=

S011 1 U=

S0110 0 U=

1

0 0

0

(^11)

XXXU=

NAME of state OUTPUT when in thisstate

Heavy circleMeans INITIAL^ state^0 INPUTcausingtransition

Designing our lock …^ • ^ Need an initial state; call it SX.^ • ^ Must have a separate state for each stepof the proper entry sequence^ • ^ Must handle other (erroneous) entries

Why do thesego to S0 and S01?

L06 – FSMs 7

2/24/ Yet Another SpecificationSXS0S01U=0U=0 0 U=0^1

S011S0110U=0 1 U=1^0 1

0 1 001

IN^ Current State

Next State Unlock

0 SX^

S0^0

1 SX^

SX^0

0 S

S0^0

1 S^

S01^0

0 S

S0^0

1 S

S011^0

0 S

S

1 S

SX

0 S

S

1 S

S

All state transitiondiagrams can bedescribed by truthtables…Binary encodings areassigned to each state(a bit of an art)The truth table can thenbe simplified using thereduction techniques welearned for combinationallogic

000000 00 100 10 1 10 1 10 100 10^100100

00 1 000 00 10 1 100 10 101 00 000 00 10 1 1 The assignment of codes tostates can be arbitrary, however,if you choose them carefully youcan greatly reduce your logicrequirements.

6.004 – Spring 2009^

2/24/ Valid State Diagrams

S1 •  Arcs leaving a state must be: •  (1) mutually exclusive –  can’t have two choices for a given input value •  (2) collectively exhaustive –  every state must specify what happens for each possible inputcombination. ā€œNothing happensā€ means arc back to itself.

1 S3 0 11 00 S2^01 MOORE Machine:Outputs on States

1/1 S1 S31/00/0 0/1S21/0 MEALY^ Machine:Outputs on Transitions

0

0/

L06 – FSMs 13

6.004 – Spring 2009^

2/24/

What’s My Transition Diagram?

vs.

0= "

o^1 You Win!

OFF,1=ON?111" =Surprise!

  • ^ If you know NOTHING about the FSM, you’re never sure! • ^ If you have a BOUND on the number of states, you can discover itsbehavior:K-state FSM: Every (reachable) state can bereached in < k steps.BUT ... states may be equivalent!

L06 – FSMs 14

6.004 – Spring 2009^

2/24/

FSM Equivalence

vs.

ARE THEY DIFFERENT?NOT in any practical sense! They are EXTERNALLYINDISTINGUISHABLE, hence interchangeable.FSMs

EQUIVALENT

iff every input sequence

yields identical output sequences.ENGINEERING GOAL:• HAVE an FSM which

works...

• WANT simplest (ergo cheapest) equivalent FSM.

L06 – FSMs 15

6.004 – Spring 2009^

2/24/

Lets build an

Ant

• ^ SENSORS: antennae L and R, each 1 if incontact with something. • ^ ACTUATORS: Forward Step F, ten-degreeturns TL and TR (left, right).

8 legs? GOAL: Make our ant smart enough to get out of a maze like:STRATEGY: "Right antenna to the wall"

L06 – FSMs 16

6.004 – Spring 2009^

Lost in space^? 2/24/

Action: Go forward until we hit something.^ LOSTL+RF _ _L R ā€œlostā€ is theinitial state

Figure by MIT OpenCourseWare.

L06 – FSMs 17

Bonk! 2/24/ LOSTL+RF _ _L R

L+R RCCWTL _ _L R

Action: Turn left (CCW) until we don’t touch anymore

6.004 – Spring 2009^

2/24/ A little to the right…LOSTF

L+R RCCWL+RTL R Wall1_TR,FR _ _L R

_ _L R Action: Step and turn right a little, look for wall

L06 – FSMs 19

2/24/ Then a little to the leftLOSTF

L+R RCCWL+RTL R Wall1_TR,FR _ _L R

_ _L R^

Wall2TL,FL _ _L R _L R

Action: Step and turn left a little, till not touching (again)

6.004 – Spring 2009^

2/24/ Dealing with cornersLOSTF

Wall2TL,F L+R RCCWL+RLTL R Wall1_TR,FR _ _L R

_ _L R^

_ _L R

_L R R _RCornerTR,F

Action: Step and turn right until we hit perpendicular wall

L06 – FSMs 25

Ant Schematic 2/24/

6.004 – Spring 2009^

RoboantĀ® 2/24/

Mazeselection

FSM statetable Statusdisplay

Plan viewof mazeSimulationcontrols

Featuring the new Mark-II ant: can add (M),erase (E), and sense (S) marks along its path.

L06 – FSMs 27

2/24/ Housekeeping issues…ROMorgatesNEXT inputs^ STATE

outputs s s

1. Initialization? Clear the memory?2. Unused state encodings?- waste ROM (use PLA or gates)- what does it mean?- can the FSM recover?3. Choosing encoding for state?4. Synchronizing input changes withstate update?

IN CLK

U Now, that’s a funnylooking state machine

6.004 – Spring 2009^

2/24/ Twisting you Further…

-^ MORE THAN ANTS:Swarming, flocking, and schooling can resultfrom collections of very simple FSMs• PERHAPS MOST PHYSICS:Cellular automata, arrays of simple FSMs,can more accurately model fluilds thannumerical solutions to PDEs• WHAT IF:We replaced the ROM with a RAM and haveoutputs that modify the RAM?... You'll see FSMs for the rest of your life!

Did we all descend from FSMs??? I prefer to think we^ ascended …