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Finite State Machines

CT101 – Computing Systems

FSM Overview

• F inite S tate M achine is a tool to model the desired

behavior of a sequential system.

• The designer has to develop a finite state model of

the system behavior and then designs a circuit that

implements this model

• A FSM consists of several states. Inputs into the

machine are combined with the current state of the

machine to determine the new state or next state

of the machine.

• Depending on the state of the machine, outputs are

generated based on either the state or the state and

inputs of the machine.

FSM Representation

• FSM = (X, Y, Q, f, g)

• If there is no state in the Q range (Q≡Ø, the circuitry

has no history), then:

• g: X x Ø->Ø, there is no state transition function
• f: X x Ø -> Y is becoming f: X -> Y
• In this case, the FSM is equivalent to an CLC
• FSM| (^) Q≡Ø = CLC = (X, Y, f)

Asynchronous vs. Synchronous

• Async FSM – the next state becomes the

present state after the delays through the

delay elements

• Sync FSM – obtained by replacing the delay

elements di with memory elements

(registers). The wi bits of the next state will

be written in the registers (memory

elements) only on the clock (on edge or

level) is applied.

Sync FSM with delayed outputs

Y(t) Y(t+1)

CLC Q+(t)

Registers Q(t)

CLK

t t+1 t+

Q(t+1) = Q+(t)

X(t)

Synchronous FSM with delayed outputs

The next state is assigned as present state on the next clock cycle. Similarly, we can proceed with the outputs, obtaining the delayed state machine. Each bit of the output is passed through a memory element.

Timing diagram for synchronous

FSM

Y(t+1)

Q(t+1)

Y(t)

X(t+1)

T (^) 2T

State interval

X(t)

Y(t-1)

Transient interval

Stable interval

t t+ Input

Immediate Output

State Transition

Delayed Output

Q(t) Z(t+1) := W(t)

Y(t+1) := Y(t)

Transient interval

Stable interval

State interval

Z(t+2) := W(t+1)

Y(t+2) := Y(t+1)

W(t) = g[X(t),Z(t)] Y(t) = f(X(t),Z(t)] t+

W(t+1) = g[X(t+1),Z(t+1)] Y(t+1) = f(X(t+1),Z(t+1)]

Clock

Timing diagram for synchronous FSM Docsity.com

State tables

• Similar to the truth table
• Doesn’t contain the system clock when

specifying its transitions (it is implicit that

transitions occur only when allowed by clock)

• Unless different stated, all the transitions are

occurring on the positive edge of the clock

Present

State

Inputs Next

State

Outputs

Alarm clock state table

• When you are asleep and alarm goes on, you go from being asleep to being awaked in bed; you also turn off the alarm
• The next two rows encode your actions:
  • You get up
  • You go back to sleep
• This table doesn’t cover what you wouldn’t do…(i.e. if you are asleep and the alarm doesn't go off, you remain asleep, etc..)

Present State

Alarm Weekday Next State Turn off alarm

Asleep On X Awake in bed

Yes

Awake in bed

Off Yes Awake and up

No

Awake in bed

Off No Asleep No

State diagram

• Graphical representation of the state table
• Each state is represented by a circle vertex
• Each row of the state table is represented as a directed arc

from present state vertex to the next state vertex

• In this diagram, the outputs are associated with the states

Alternative state diagram

• The outputs are associated with the arcs
  • An output of 1 represents that “turn off the alarm” is Yes
  • By convention , inputs which are don’t care and inactive outputs are not shown.

Mealy FSM

• Output is dependent on the inputs and the current state
• Delayed output FSM implies the fact that the calculated output for an input applied at time t is assigned at time t+1. This is correct at an Mealy FSM

Clock

X(t)

Registers Bank 1

Q(t+1) = Q+(t)

CLC f

CLC g

Y(t)

Y(t) = f[X(t), Q(t) Q+(t) = g[(X(t), Q(t)] Q(t+1) = Q+^ (t)

Mealy with immediate output

Q(t)

X(t)

Q(t)

Registers Bank 1

Q(t+1) = Q+(t)

CLC f

CLC g

X(t)^ Y(t)

Y(t) = f[X(t), Q(t) Q+(t) = g[(X(t), Q(t)] Q(t+1) = Q+(t) Y(t+1) := Y(t)

Mealy with delayed output

Registers Bank 2

Y(t) Y(t+1) := Y(t)

X(t) Q(t)

Q(t)

Moore FSM

Registers Q(t) (^) Bank 1 CLC g

Clock

X(t)

Q+(t) = g[(X(t), Q(t)] Q(t+1) = Q+(t) Y(t+1) := f[Q+(t)]

Moore with immediate output

CLC2 Y(t+1) f

Q(t+1) = Q+(t)

X(t) Registers Q(t) (^) Bank 1 CLC g

Clock

Q+(t) = g[(X(t)] Q(t+1) = Q+(t) Y(t+2) := f[Q+(t)]

Moore with delayed output

CLC2^ Y(t+2) f

Q(t+1) = Q+(t)

Registers Bank 2

• Output is dependent only on the current state
• Immediate Moore FSM: the output is obtained with a clock period delay, since the then the next state becomes present state
• Delayed Moore FSM: the output is actually obtained with two clock period delay, because of the Registers Bank 2

Mealy machine diagram

• Self arcs must be shown (because the output

values are shown on the arcs)

• Can be more compact than Moore machine,

especially when two or more arcs with

different output values go into the same

state