Flip Flops: Understanding Edge-Triggered and Level-Sensitive Latch and Flip-Flop Circuits, Slides of Digital Logic Design and Programming

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Flip Flops

Not a gymnastic movement.

Class 20 – Flip Flops

• Definitions
• Latches
  • Set-Reset – SR
  • The D Latch
• Material from section 5-3 of text

Flip-flops

• Constructed in such a way that they are edge-triggered.
• This is in contrast to latches which are level sensitive and said to be transparent.
• There are two general methodologies for making flip-flops - Edge-triggered - Master-Slave

Master Slave Flip-flops

• The Master-Slave SR Flip-flop
• And its operation

A HDL model of the same

• The SR latch model with control input C

ENTITY SR_latch IS PORT (S,R,C : IN BIT; Q, Q_bar : OUT BIT); END SR_latch; ARCHITECTURE one OF SR_latch IS SIGNAL CS,CR : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN CS <= S nand C after 1 ns; CR <= R nand C after 1 ns; Q_int <= CS nand Q_bar_int after 1 ns; Q_bar_int <= CR nand Q_int after 1 ns; Q <= Q_int; Q_bar <= Q_bar_int; END one;

A testbench to provide stimulus

• tb model
• Links in the latch in a master slave manner

ENTITY tb IS END tb; ARCHITECTURE one OF tb IS SIGNAL Clk,nClk,S,R,D : BIT; SIGNAL i1,i2 : BIT; SIGNAL SRq,SRqbar : BIT; COMPONENT SR_latch PORT (S,R,C : IN BIT; END COMPONENT; FOR ALL : SR^ Q,Q_bar : OUT BIT);_latch USE ENTITY work.sr_latch(one); BEGIN -- Clk <= not Clk after 10 ns; gen clock signals nClk <= not Clk after 1 ns; -- wire in master slave FF SRm : SR_latch PORT MAP(S,R,Clk,i1,i2); SRs : SR_latch PORT MAP(i1,i2,nClk,SRq,SRqbar); PROCESS BEGIN S<='0'; R<='0'; WAIT FOR 10 ns; S<='1'; R<='0'; WAIT FOR 20 ns; S<='0'; R<='0'; WAIT FOR 10 ns; S<='0'; R<='1'; WAIT FOR 20 ns; S<='0'; R<='0'; WAIT FOR 50 ns; S<='1'; R<='0'; WAIT FOR 20 ns; S<='0'; R<='0'; END PROCESS;^ WAIT FOR 10 ns;^ WAIT; END one;

The D Flip-flop

• The D can be constructed from the use of a D latch and an SR latch.

For a positive edge FF

• Add an inverter to the clock input

HDL simulation

• Results now for the D F/F
• Remember the delays

Flip flop with preset and clear

• Allows direct setting of state of flip-flop.
• When initially powered state of flip-flop is unknown. The sets the FF to a known state.