Sequential Circuits: SR Latch and Flip-Flops, Slides of Technology

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SEQUENTIAL CIRCUITS

SR LATCH

SR LATCH (NOR GATE)

 The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output 0 s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values

SR LATCH (NOR GATE)

SR LATCH (NAND GATE)

 The inputs are generally designated S and R for Set and Reset respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit (or active low).  When the S and R inputs are both high, feedback maintains the Q outputs to the previous state.

SR LATCH (NAND GATE)

 The R = S = 0 combination is called a restricted combination or a forbidden state because, as both NAND gates then output 1 s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go high simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition).

SR LATCH (NAND GATE)

CLOCK

CLOCK

 Logic elements like latches and flip-flops require a periodic waveform to establish the rate at which the logic updates; all synchronous logic depends on the signal integrity of the clock to perform as expected. Depending on the components , status updates may occur on the low-to-high voltage transition (rising edge) or vice versa (falling edge). Selection of the clock speed depends on the slowest possible propagation path across the circuit , resulting from both material selection and the efficiency of the board design.

DIFFERENCE BETWEEN LATCH AND FLIP FLOP

DIFFERENCE BETWEEN LATCH AND FLIP FLOP

 The major difference between flip-flop and latch is that the flip-flop is an edge- triggered type of memory circuit while the latch is a level-triggered type. It means that the output of a latch changes whenever the input changes. On the other hand, the flip flop only changes its state whenever the control signal goes from low to high and high to low.

LATCH

 A latch is an electronic device that changes its output immediately on the basis of the applied input. One can use it to store either 0 or 1 at a specified time. A latch contains two inputs- SET and RESET , and it also has two outputs. They complement each other. One can use a latch for storing one bit of data. It is a memory device- just like the flip-flop. But it is not synchronous, and it does not work on the edges of the clock like the flip-flop.