Engineering Document: Sequential Logic Circuits with Karnaugh Maps and FlipFlops, Slides of Electrical Circuit Analysis

Download Engineering Document: Sequential Logic Circuits with Karnaugh Maps and FlipFlops and more Slides Electrical Circuit Analysis in PDF only on Docsity!

Engineering 43

Sequential

(FlipFlop) Logic

But First… WhiteBoard Work

• For the Truth Table Shown

at right

• Construct the Karnaugh Map
• Write The Minimized Function Q(A,B,C,D)
• Draw the Logic Circuit
• Notice “1’s” in Rows
• 1, 5, 9, 13, 14, 15
• Need only put “1’s” in these locations; other cells Assumed to be Zero

Row (^) A B C D Q (^0 0 0 0 0 ) (^1 0 0 0 1 ) (^2 0 0 1 0 ) (^3 0 0 1 1 ) (^4 0 1 0 0 ) (^5 0 1 0 1 ) (^6 0 1 1 0 ) (^7 0 1 1 1 ) (^8 1 0 0 0 ) (^9 1 0 0 1 ) (^10 1 0 1 0 ) (^11 1 0 1 1 ) (^12 1 1 0 0 ) (^13 1 1 0 1 ) (^14 1 1 1 0 ) (^15 1 1 1 1 )

Stretchable Blank Map

AB\CD 00 01 11 10

More… WhiteBoard Work

• Implement This Function using ONLY

NAND Gates

• An Example of NAND-Gate Synthesis
  • NANDS are easier to construct than ANDs, ORs,

NORs

• NANDs are the preferred gate for logic circuits

F = ACD + ABC D + A B

Sequential Circuit

• A sequential circuit

consists of a

feedback path,

and employs

some memory

elements

• [Sequential circuit] = [Combinational logic] +

[Memory Elements]

Combinational logic

Memory elements

Combinational outputs Memory outputs

External inputs

Synchronous vs Asynchronous

• Almost all Logic “Chips” Include a Clock
• The Clock helps to “Synchronize” the

Operation of the Circuits.

• The “Clock” is simply a very regular Hi/Lo

Pulse train 

• Logic Forms are divided into two groups:
  • SYNCHRONUS → Depend on Clock
  • A synchronous → NO Clock-Dependency

NAND based SR FlipFlop

• Cross-coupled NAND gates
  • Similar to inverter pair, with capability to force Q

to 0 (reset=0) or 1 (set=0)

R'

S'

Q

Q

Q'

S'

R'

NOR notes

 Any HI input → LO output

• Any HI → LO

 All LO inputs → HI output

• All LO → HI

 Any LO input → HI output

• Any LO → HI

 All HI inputs → LO output

• All HI → LO

NAND notes

State Behavior of SR FlipFlop

• Transition Table
• Sequential (output depends on history when

inputs R=0, S=0) but asynchronous

R

S

Q

Q'

S R Q (^) n-1 Qn 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X

hold

reset

set

not allowed

characteristic equation Q (^) n = S + R’∙Q (^) n-

Qn- 1 \SR 00 01 11 10

0 0 0 X 1

1 1 0 X 1

REset SET

Clocked SR FlipFlop

• Control times when

R and S

inputs matter

• Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored
• Ensure R & S stable before utilized (to avoid transient R=1, S=1)

enable'

S'

Q'

Q

R' R

S

Set Reset

S' R' enable' Q Q'

100

Clocked SR FlipFlops

• NOR-NOR

Implementation

• Truth

Table

• For NOR: any - Hi→LO; ALL-LO→Hi

enable'

S'

Q'

Q

R' R

S

R’ S’ En’ R S Qn 0 0 0 1 1 NotAllowed 0 1 0 1 0 Reset to 0 1 0 0 0 1 Set to 1 1 1 x 0 0 Qn− x x 1 0 0 Qn− x → Don’t Care

SR FlipFlop Clock-Overide

• Sometimes Need to Set or Reset the

FlipFlop withOUT Regard to the Clock

• Note the position of Pr & Cl on the

3 rd^ -Stage ORs (any Hi→Hi)

• Ensures Pr & Cl OverRide R, S, & C

Edge Triggered D FlipFlop

• sensitive to

inputs only near

edge of clock

signal (not

while steady )

Q

D

Clk=

R

S 0

D’

0

D’ (^) D

Q’

holds D' when clock goes low

holds D when clock goes low

Edge Triggered D FlipFlop

• 4-NAND,

1-NOT

implementation

• Truth Table for

All Postive-Going

Edge D-FF’s

• NAND:
  • any LO → Hi
  • All HI → LO

CLK D Q (^) n

0 x Qn−

1 x Qn−

↑ 0 0

↑ 1 1

Edge Triggered JK FlipFlop

• A “Toggling” Flip Flop
  • Under A certain Control-Set: Q → Q’
    • Notice that Q does NOT go HI-for-sure or LO-for-sure, and it does NOT remain STEADY
• A NAND Nest:
  • Circuit Symbol