Forwarding, Exams of Computer Architecture and Organization

Download Forwarding and more Exams Computer Architecture and Organization in PDF only on Docsity!

Forwarding

 Now, we’ll introduce some problems that data hazards can cause for our

pipelined processor, and show how to handle them with forwarding.

The pipelined datapath

Read address Instruction memory Instruction [31-0] Address Write data Data memory Read data MemWrite MemRead 1 0 MemToReg 4 Shift left 2 Add ALUSrc Result Zero ALU ALUOp Instr [15 - 0] RegDst Read register 1 Read register 2 Write register Write data Read data 2 Read data 1 Registers RegWrite Add Instr [15 - 11] Instr [20 - 16] 0 1 0 1 IF/ID ID/EX EX/MEM Control MEM/WB M WB WB P C 1 0 PCSrc Sign extend EX M WB

 Here is the example instruction sequence used to illustrate pipelining on

the previous page.

lw $8, 4($29) sub $2, $4, $ and $9, $10, $ or $16, $17, $ add $13, $14, $

 The instructions in this example are independent.

— Each instruction reads and writes completely different registers.

— Our datapath handles this sequence easily, as we saw last time.

 But most sequences of instructions are not independent!

Our examples are too simple

An example with dependencies

sub $2, $1, $

and $12, $2, $

or $13, $6, $

add $14, $2, $

sw $15, 100($2)

sw $15, 100($2) IF ID EX MEM WB add $14, $2, $2 IF ID EX MEM WB or $13, $6, $2 IF ID EX MEM WB and $12, $2, $5 IF ID EX MEM WB sub $2, $1, $3 IF ID EX MEM WB

Clock cycle

 The SUB instruction does not write to register $2 until clock cycle 5. This

causes two data hazards in our current pipelined datapath.

— The AND reads register $2 in cycle 3. Since SUB hasn’t modified the

register yet, this will be the old value of $2, not the new one.

— Similarly, the OR instruction uses register $2 in cycle 4, again before

it’s actually updated by SUB.

Data hazards in the pipeline diagram

sw $15, 100($2) IF ID EX MEM WB add $14, $2, $2 IF ID EX MEM WB or $13, $6, $2 IF ID EX MEM WB and $12, $2, $5 IF ID EX MEM WB sub $2, $1, $3 IF ID EX MEM WB

Clock cycle

 The ADD instruction is okay, because of the register file design.

— Registers are written at the beginning of a clock cycle.

— The new value will be available by the end of that cycle.

 The SW is no problem at all, since it reads $2 after the SUB finishes.

Things that are okay

A fancier pipeline diagram

IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg sub $2, $1, $ and $12, $2, $ or $13, $6, $ add $14, $2, $ sw $15, 100($2) Clock cycle 1 2 3 4 5 6 7 8 9

A more detailed look at the pipeline

 We have to eliminate the hazards, so the AND and OR instructions in our

example will use the correct value for register $2.

 When is the data is actually produced and consumed?

 What can we do?

or $13, $6, $2 IF ID EX MEM WB and $12, $2, $5 IF ID EX MEM WB sub $2, $1, $3 IF ID EX MEM WB

Clock cycle

Bypassing the register file

 The actual result $1 - $3 is computed in clock cycle 3, before it’s needed

in cycles 4 and 5.

 If we could somehow bypass the writeback and register read stages when

needed, then we can eliminate these data hazards.

— Today we’ll focus on hazards involving arithmetic instructions.

— Next time, we’ll examine the lw instruction.

 Essentially, we need to pass the ALU output from SUB directly to the AND

and OR instructions, without going through the register file.

or $13, $6, $2 IF ID EX MEM WB and $12, $2, $5 IF ID EX MEM WB sub $2, $1, $3 IF ID EX MEM WB

Clock cycle

Where to find the ALU result

 The ALU result generated in the EX stage is normally passed through the

pipeline registers to the MEM and WB stages, before it is finally written to

the register file.

 This is an abridged diagram of our pipelined datapath.

Instruction memory Data memory 1 0 PC ALU Registers Rd Rt 0 1 IF/ID ID/EX EX/MEM MEM/WB

Outline of forwarding hardware

 A forwarding unit selects the correct ALU inputs for the EX stage.

— If there is no hazard, the ALU’s operands will come from the register

file, just like before.

— If there is a hazard, the operands will come from either the EX/MEM

or MEM/WB pipeline registers instead.

 The ALU sources will be selected by two new multiplexers, with control

signals named ForwardA and ForwardB.

IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg sub $2, $1, $ and $12, $2, $ or $13, $6, $

Simplified datapath with forwarding muxes

ForwardA Instruction memory Data memory 1 0 PC ALU Registers Rd Rt 0 1 IF/ID ID/EX EX/MEM MEM/WB 0 1 2 0 1 2 ForwardB

Detecting EX/MEM data hazards

 So how can the hardware determine if a hazard exists?

 An EX/MEM hazard occurs between the instruction currently in its EX

stage and the previous instruction if:

1. The previous instruction will write to the register file, and

2. The destination is one of the ALU source registers in the EX stage.

 There is an EX/MEM hazard between the two instructions below.

 Data in a pipeline register can be referenced using a class-like syntax.

For example, ID/EX.RegisterRt refers to the rt field stored in the ID/EX

pipeline.

IM Reg DM Reg IM Reg DM Reg

sub $2, $1, $

and $12, $2, $

EX/MEM data hazard equations

 The first ALU source comes from the pipeline register when necessary.

if (EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd = ID/EX.RegisterRs)

then ForwardA = 2

 The second ALU source is similar.

if (EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd = ID/EX.RegisterRt)

then ForwardB = 2

IM Reg DM Reg IM Reg DM Reg

sub $2, $1, $

and $12, $2, $