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UNIVERSITY OF CALIFORNIA
College of Engineering Electrical Engineering and Computer Sciences Department
145M Microcomputer Interfacing Lab
Final Exam Solutions May 20, 1991
1A Glitch^ (of a D/A converter) Brief erroneous spike that occurs in the output of a D/A converter when >1 input bits change at slightly different times. [Note: the critical element here is that the bits change at different times- the statement that more than one bit changes was insufficient]
1B Handshaking^ (between any sender and receiver):^ Communication procedures used to ensure that both sender and receiver are ready before the transaction and that the data have been successfully transferred. For full handshaking the four steps are: the sender is ready, the receiver is ready, the data have been asserted, the data have been taken. [Note: the last two steps were good for full credit]
1C Frequency Aliasing:^ Erroneous lower frequencies that arise when a waveform is periodically sampled at less than twice its maximum frequency. [3 points off if answer was “one-half” rather than “twice”] [4 points off if sampling frequency not mentioned]
1D Sample and Hold Amplifier:^ Analog device that either amplifies an input signal or holds its output at a constant value, depending on a digital control signal. [2 points off if sample mode not mentioned]
1E Settling time^ (of a D/A converter): The time required for the output of the converter to reach its final value (within a specified error band) after a large change in the input.
1F Two’s Complement^ (the operation):^ Procedure for complementing all the bits of an number and adding one. Adding the two’s complement of a number produces the same result as subtracting the number.
1G Formants^ of^ Vowels:^ Resonance^ peaks^ in^ the^ FFT^ frequency^ spectrum^ (amplitude^ vs. frequency) determined in part by the shape of the oral cavity.
2A
micro- computer
timer
Binary input port
Binary output port
A/D
converter
Start conversion
10 μs one-shot
Sample and hold
External memory unit
Data^16
Adder
Address
Zero
Increment
R/W
CS
Data ready
delay
OR
Anti- aliasing filter
disk drive
screen
keyboard
[2 points off if sample-and-hold control not shown] [5 points off if computer is in data acquisition loop]
2B PROGRAM: 1 ask for N, T, file name 2 set R/ W low for writing to external memory unit 3 clear adder 4 setup_go(T,N) 5 wait until counter(2) equals zero 6 set R/ W high for reading from external memory unit 7 clear adder 8 open file 9 use binary output to pulse external memory unit CS 10 read data lines of external memory unit into binary input port (transparent mode) 11 write data to file 12 increment adder with delayed CS pulse 13 loop back to step 9 N times EXTERNAL CIRCUIT (actions during program step 5 – data acquisition): 1 9513 timer pulse starts 10 μs one-shot which puts S/H into hold mode 2 9513 timer pulse starts A/D conversion 3 At end of conversion, A/D converter Data Ready pulse writes data into external memory via CS line 4 After short delay, the Data Ready pulse increments the adder EXTERNAL CIRCUIT (actions during program steps 9-13 – data retrieval) 1 binary output reads external memory unit via CS pulse 2 external memory unit data lines are read into binary input port 3 after a short delay, adder is incremented [4 points off if external circuit function not described]
2C fmax^ = 100 kHz (limited by 10 μs A/D conversion time. fmin^ = 1 MHz/
(^32) = 1/4000 s = 250 μHz.
2D Nmax^ = 1.05 x 10
(^6) (limited by memory size). T = 10.5 s.
2E 1 step size (average) = 20 V/
(^16) = 305 μV. Specification is that individual steps are 1 LSB ± 4 LSB and could vary from –3 to +5 LSB. The answer that the step sizes could be in error by as much as 1.22 mV was accepted.
2F A low-pass filter with a sharp cut-off just below 500 Hz.
3A^1 Remove frequency components above 1/2 the sampling frequency with a low-pass filter 2 Trigger A/D converter, sample analog input, and store converted output xj 3 Perform the digital filter operation yi = ΣAjxi–j + ΣBjyi–j 4 Convert the result with a D/A converter – this is the analog output
3B^1 set up microphone and amplifier 2 use anti-aliasing filter (low pass with cut-off at about 20 kHz) 3 sample voice signal at about 40-60 kHz 4 store data in memory 5 output data to D/A at the same rate as sampled 6 amplify output for speaker [1 point off if no microphone or amplifier] [2 points off if no microphone, amplifier, or speaker] [3 points off if no microphone, amplifier, or anti-alias filter] [4 points off if no microphone, amplifier, anti-alias filter, output amp, or speaker]
3C^1 zero the digital timer 2 start the FFT 3 when the FFT is finished, read the timer 4 convert the timer count to suitable time units Note: this procedure could be used to time any process
For the IIR approach, the complex Fn (t+∆t) are derived from the Fn (t) and the data fk as follows
F (t)n F (t+n ∆t)
f (^) k shift register f 0 f (^512) exp(i2πn/512)
* *^ *
- these 4 elements are replicated for each Fn
5C For FIR approach need 512 for real part, 512 for imaginary part, and 512 to take square root of sum of squares (modulus) – 1536 in all. Each of the first two processors must make 512 multi- plications and additions. For IIR approach need 512 to (i) add real part of new term, (ii) subtract real part of last term, (iii) phase shift, and 512 for similar operations for imaginary coefficients, and and 512 to take square root of sum of squares (modulus) – 1536 in all. Each processor only needs to make a few multiplications and additions.
145M Numerical Grades:
7/8 x Lab Midterm Final Total Averages 662 95 162 918 (B+) rms 42 7 24 63
145M Letter Grade Distribution
Letter Grade Course Totals (1000 max)
A+ 990 A 959, 967 A– 933, 945, 947, 947
B+ 912, 913, 924 B none B– none
C 789, 797
