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EECS31L/CSE31L
Winter 2009
Graphical Tutorial for Xilinx ISE and
ModelSim
1. Introduction
This tutorial aims to give a step by step introduction to creating a project in Xilinx ISE and simulating it on ModelSim. The design is implemented in a given VHDL file.
2. Pre-requisites
Xilinx ISE and ModelSim should be installed and integrated on the system. You should also have the template files provided to you as part of the assignment 1.
3. Lab Assignments
All of your lab assignments will be from the examples of textbook VHD L fo r Digita l Desig n by Vahid and Lysecky. The description of your assignments will also be made available to you through EEE. The templates and the first assignment are available on EEE at Dropbox Æ AssignmentName Æ CourseFiles.
4. Project creation
- In Xilinx ISE, every design is described by a project. Hence, the first step involves starting a new project. Open New project creation wizard from the File Æ New Project menu. This should open a dialog box like shown in Figure 1. You would notice that the default location of your project directory is C:\Xilinx\10.1 (or the directory you installed Xilinx ISE WepPACK). However, it is generally a good idea to change it to something personal like C:\myProjDir\ as in the figure.
(^1) Xilinx WebPACk and Modelsim installation guide will be uploaded to EEE
Figure 1: New project creation wizard
The Top-Level Source Type should be selected as HDL since we will describe our design using VHDL. Add the project name in the text box entry.
- The next dialog box will be something like in Figure 2.
Figure 2: New project creation wizard -Device Properties
We will not be running our design on a real hardware. Therefore, most of the details here regarding device properties can be ignored. However, make sure that the Synthesis Tool is selected as XST (VHDL/Verilog) , Simulator as
Figure 4: New project created
5. Design Implementation
You may now add the architectural description in the VHDL file. To check for the correctness of your VHDL code, you may consider checking the syntax. This can be done by clicking this option in the lower left panel of the processes. This is shown in Figure 5.
Figure 5: Syntax checking
6. Simulation
- Once you have implemented your design in the VHDL file and checked for the syntax correctness, you should test your design for its behavior. This can be done by simulating your design with various inputs. Double click Create New Source to create a testbench for your design. Select VHDL Test Bench as shown in Figure 6 while creating new file. You will then be asked to associate this test bench with a file. Since you have created only a single file till now, this list will have only one file. Select that file and finish this wizard. A file will be created and you may add your test vectors in the file.
Figure 6: Adding Testbench to the project
- To run the simulation for your design using this new test bench, select Behavioral Simulation as in Figure 7.
Figure 7: Selecting Behavioral Simulation Select your testbench file in the upper left panel. The lower panel will then
the testbench to test it again.
- If your design passes the simulation, you can repeat the above steps to implement another description of your design. You will be required to add files for design description and for testbench.
7 Submission
After finishing your assignment, you need to upload only the moodified template files in the EEE. The dropbox for the first assignment is Dropbox Æ AssignmentName Æ AssignmentSubmission. You are NOT required to submit your testbench or your project.
8 Further Reading
There are many good tutorials over the web. Xilinx also has some tutorial documents for reference.
- Quick Start tutorial : http://www.xilinx.com/itp/xilinx10/books/docs/qst/qst.pdf
- In-depth tutorial : http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm
