Tools for Sequential Logic Design: MS Visio, ModelSim, Xilinx ISE, Altera Quartus II, Slides of Digital Logic Design and Programming

An overview of the logic design tools used in the sequential logic design course, including ms visio for creating clean schematics, modelsim for hdl simulation, xilinx ise for fpga implementation, and altera quartus ii for quartus ii development. The document also includes instructions on how to use these tools for various tasks such as creating new projects, adding files, choosing devices, and programming the fpga.

Typology: Slides

2012/2013

Uploaded on 03/18/2013

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Sequential Logic Design
Lecture #2
Agenda
1. Logic Design Tools
Announcements
1. n/a
Docsity.com
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Download Tools for Sequential Logic Design: MS Visio, ModelSim, Xilinx ISE, Altera Quartus II and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Sequential Logic Design

Lecture

  • Agenda
    1. Logic Design Tools
  • Announcements
    1. n/a

Logic Design Tools

  • MS Visio
    • a generic drawing program.
    • industry is converging on this program for documentation.
    • has built in shape libraries, including analog/digital logic.
    • we’ll use it for this class to create clean schematics.

Logic Design Tools

  • ModelSim (by Mentor Graphics)
    • an HDL Simulation (VHDL and Verilog)
    • widely used in industry
    • has color-coded text editing for keywords
    • has console for verification reporting
    • we’ll use for homework & before FPGA synthesis.

Logic Design Tools

  • ModelSim (^) Simulation Waveform

Project Navigator

Console

Logic Design Tools

  • Xilinx ISE
    • Integrated Software Environment (ISE)
    • Implementation tool
    • compile / simulate
    • synthesis
    • technology mapping
    • place and route
    • back annotation for post-route simulation and timing verification
    • can do similar simulation as in ModelSim
    • this is where we :
      • select FPGA to target
      • assign signal pins
      • set timing constraints
      • set placement constraints
      • set routing constraints
      • generate programming file
      • download file to FPGA, EEprom, or CPLD using the JTAG interface.

Logic Design Tools

  • Xilinx ISE

Sources Window

Processes Window

Edit/View Window

Logic Design Tools

  • Xilinx ISE

HDL or Schematic Entry

Routing Editor

Altera Quartus II Development Tool

New Project Wizard

Creation of new project

Choose device family and specific

device

Electronic Design Automation Tools

Quartus II display of created project

Processing>Start Compilation