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Hardware Aspects Part 1-Microcontroller 8051-Lecture Slides, Slides of Microcontrollers

National Institute of Industrial EngineeringMicrocontrollers

Kumar Saxena delivered this lecture for Microcontroller course at National Institute of Industrial Engineering. Its main points are: Hardware, Aspects, On-chip, Memory, Code, Data, Timers, Serial, Port, Control, Signals, Bus

Typology: Slides

2011/2012

Uploaded on 07/07/2012

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Hardware Aspects
MCS-51 is a family of MCs by Intel and other
‘second sources‘
8051 has the following features
4K bytes ROM (factory mask able)
128 bytes RAM
Four 8-bit I/O Ports
Two 16-bit timers
Serial interface
64K external code memory space
64K external data memory space
Boolean processor (Operates on single bits)
210 bit-addressable locations
4 µsec multiply/divide
docsity.com
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Download Hardware Aspects Part 1-Microcontroller 8051-Lecture Slides and more Slides Microcontrollers in PDF only on Docsity!

MCS-51 is a family of MCs by Intel and other

‘second sources‘

8051 has the following features

4K bytes ROM (factory mask able)

128 bytes RAM

Four 8-bit I/O Ports

Two 16-bit timers

Serial interface

64K external code memory space

64K external data memory space

Boolean processor (Operates on single bits)

210 bit-addressable locations

4 μsec multiply/divide

PART

NUMBER

ON-CHIP

CODE

MEMORY

ON-CHIP

DATA

MEMORY

TIMERS

8051 4K ROM 128 bytes 2

8031 0K 128 bytes 2

8751 4K EPROM 128 bytes 2

8052 8K ROM 256 bytes 3

8032 0K 256 bytes 3

8752 8K EPROM 256 bytes 3

Other members of MCS-51 family of MCs

These features can be mentioned as a block

diagram (p.t.o.)

Read-only memory

Erasable Programmable

Read-only memory

P3.
P3.
P3.
P3.
P3.
P3.
P3.
P3.
P1.
P1.
P1.
P1.
P1.
P1.
P1.
P1.
P0.
P0.
P0.
P0.
P0.
P0.
P0.
P0.
ALE
PSEN
EA
RST
XTL 1
XTL 2
12 MHz
30 pF
30 pF
VCC
VSS
AD
AD
AD
AD
AD
AD
AD
AD
A
A
A
A
A
A
A
A
RD
WR
T
T
INT
INT
TXD
RXD
P2.
P2.
P2.
P2.
P2.
P2.
P2.
P2.

 (8*4) 32 I/O port lines

in 8xxx MC

 24 of these lines are

dual purpose in 8xx

 26 of these lines are

dual purpose in 8xx

  • Port 0: Dual Purpose, - General purpose I/O for min. comp. Design - Alternatively serves as multiplexed address

and data bus for external devices

  • Port 1: Dedicated I/O port. (xxx1 MC)
  • Port 2: Dual Purpose, - General purpose I/O for min. comp. Design - Alternatively, Address lines for accessing

external code memory or >256 bytes of

external data memory

  • Port 3: Dual Purpose, - General purpose I/O - Alternatively related to special features of

MCs

P0.7 - P0.

(AD7 - AD0)

P2.7 - P2.

(A15 - A8)

P1.7 - P1.

P3.7 - P3.

(RD#,WR#, T1, T0,

INT1#, INT0#,

TXD, RXD)

XTAL 1

XTAL 2

PSEN#

ALE

EA#

RST

Alternative functions of Ports

As 8xxx contains internal ROM and RAM,

its address, data and control signals are

internal. However, for external memory

access, these signals are available on P

as WR# and RD#

T0 / T1 : External Inputs for timers /

counters

INT0# / INT1# : Interrupt inputs

TXD : Transmit data line for serial port

RXD : Receive data line for serial port

Alternative functions of Ports

Write

to latch

Port

latch

Read

latch

Read

Pin

Internal

Pull-up

VCC

Port

Pin

8051 Internal Bus

D

Q

  • Open drain output for Port 0

when operating as an I/O pin

The 8051 implements separate memory space for

program (code) and data. Both the program (code)

and data can be internal (4K, 128 bytes) or external

(64K each).

The 8051contains 4Kbytes of ROM and 128 bytes of

RAM.

Additional 128 bytes of RAM is called Special Function

Register (S.F.R.).

The RAM is divided into three parts:

I. Register banks,

II. Bit addressable RAM and

III. Byte addressable RAM.

Memory Organization (8051)

Memory Organization (8051)

0F
1F
2A
2B
2C
2D
2E
2F
7F
0A
0C 0B
0F 0E 0D
1F 1E 1D 1C 1B 1A 19 18
2F 2E 2D 2C 2B 2A 29 28
3A
3C 3B
3F 3E 3D
4F 4E 4D 4C 4B 4A 49 48
5A
5C 5B
5F 5E 5D
6A
6C 6B
6F 6E 6D
7A
7C 7B
7F 7E 7D
Bank 3
Bank 2
Bank 1

Default register

bank for R0-R

General

purpose

RAM

Byte

address

Bit address

RAM

Bit addressable locations

F1 F
F
F4 F
F7 F6 F
E6 E5 E4 E3 E2 E1 E
E
D2 D
D6 D5 D4 D
D
B2 B1 B
B6 B5 B4 B
B
A2 A1 A
A6 A5 A4 A
A
A9 A
AA
AC AB
AF - -
9F 9E 9D 9C 9B 9A 99 98
8A
8C 8B
8F8E 8D
B9 B
BA
BC BB

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

not bit addressable

8A
8B
8C
8D
A
A
B
B
D
E
F
FF

Byte

address

Bit address

B
ACC
PSW
IP
P
IE
P
SBUF
SCON
P
TH
TH
TL
TL
TMOD
TCON
PCON
DPH
DPL
SP
P

SPECIAL FUNCTION REGISTERS docsity.com

Memory Organization (8051)

Internal RAM:

00H - 7FH  General purpose

Register

Banks

Bit

Addressable

Byte

Addressable

0 (R0 - R7)

3 (R0 - R7)

00H

07H

18H

1FH

20H

2FH

00H 07H

7FH 78H

7FH

30H