Hardware Functional Verification - Functional Verification - Lecture Slides, Slides of Computer Science

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Hardware Functional

Verification

Introduction

What this course is about?

(cont)

 To teach necessary concepts for tools of verification  Describe a process for carrying out effective functional verification  Present techniques for applying stimulus and monitoring the response of a design utilizing bus functional models  Present the importance of behavioral modeling

Prior Knowledge

 This class focuses on functional verification of hardware design using either VHDL or Verilog  Expect students to have a basic knowledge of one of these languages  Expect students to have basic understanding of digital hardware design  Class will focus more on VHDL

Why HDL Verification?

 I mentioned 60% - 80% time spent in

verification – WHY??

 Product time-to-market  hardware turn-around time  volume of "bugs"  Development costs  "Early User Hardware" (EUH)

Why HDL Verification? (cont)

 Cost of bugs over time  Longer a bug goes undetected, the more expensive it is  Bug found early (designer sim) has little cost  Finding a bug at chip/system has moderate cost  Requires more debug time and isolation time  Could require new algorithm, which could effect schedule and cause board rework  Finding a bug in System Test (test floor) requires new ‘spin’ of a chip  Finding bug in customer’s environment can cost hundreds of millions and worst of all - Reputation

Verification is a process used

to demonstrate the functional

correctness of a design. Also

called logic verification or

simulation.

What is a testbench?

 A “testbench” usually refers to the code used to create a pre- determined input sequence to a design, then optionally observe the response.  Generic term used differently across industry  Always refers to a testcase  Most commonly (and appropriately), a testbench refers to code written (VHDL, Verilog, etc) at the top level of the hierarchy. The testbench is often simple, but may have some elements of randomness  Completely closed system  No inputs or outputs  effectively a model of the universe as far as the design is concerned.  Verification challenge:  What input patterns to supply to the Design Under Verification and what isex pected for the output for a properly w ork ing designDocsity.com

Verification is on

critical path

Want to minimize

Verification Time!

Reconvergence Model

 Conceptual representation of the verification process  Most important question  What are you verifying?

Verification

Transformation

Human Factor in Verification

Process

 An individual (or group of individuals) must interpret specification and transform into correct function.

Specification Interpre- tation

RTL Coding

Verification

Automation

 Obvious way to eliminate human-

introduced errors – take the human out.

 Good in concept  Reality dictates that this is not feasible  Processes are not defined well enough  Processes require human ingenuity and creativity

Poka-Yoka

 Term coined in Total Quality Management circles  Means to “mistake-proof” the human intervention  Typically the last step in complete automation  Same pitfalls as automation – verification remains an art, it does not yield itself to well- defined steps.