Challenges in Hardware
Logic Verification
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Challenges - Functional Verification - Lecture Slides, Slides of Computer Science
These are the Lecture Slides of Functional Verification which includes Reusable Verification Components, Verilog Implementation, Implementation, Autonomous Generation and Monitoring, Input and Output Paths, Verifying Configurable Designs, Reusable Test Harness, Testcase Specific Code, Abstraction etc. Key important points are: V
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2012/2013
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Challenges in Hardware
Logic Verification
Agenda
Five Challenges in Verification
Future Verification Trends
5 Challenges in Verification
1. Better use of available simulation cycles
0 10 20 30 40 50 60 70 80 90 100 40'9843'9846'9849'9852'9803'9906'9909'9912'9915'9918'9921'9924'9927'9930'9933'9936'9939'9942'9945'9948'9951'
Bug discovery rate Docsity.com
5 Challenges in Verification
2. Specification methodology
ack will come on after the bias signal, followed in two cycles by the State Machines NOT MY Timing diagrams
5 Challenges in Verification
3. Power verification
5 Challenges in Verification
3. Power verification
Turn off units when
not in use
Verify "not in use" and no
clocking
Function Check
Low power micro-
arch design
and
design changes
Measure switching facto
in chip and in "hot areas
during sim and
benchmarks
5 Challenges in Verification
4. Error path testing in self healing systems
For all of the legal paths for which the design must be verified, there's an order of magnitude more "illegal" paths. Verification must ensure that the hardware can: Recover and continue, or Take itself off-line
5 Challenges in Verification
5. Detecting System Deadlocks
I/O I/O I/O I/O P P P P P P P P Memory P P P P P P P P Memory P P P P P P P P Memory P P P P P P P P Memory
anyServer
Queue
Interrupt
Buffer
When processor receives I/O interrupt it can't move
forward until buffer releases address X, but buffer
can't move forward until interrupt is completed....
5 Challenges in Verification
5. Choosing the right verification technology
Multiple technologies to choose from,
But, few experts in all
Random Testcase Gen FV Deterministic
5 Challenges in Verification
5. Choosing the right verification technology
Education
Experience in the verification cycle
Strong Verification career path
Continuing challenges
Future Verification Trends
Coverage Directed Testcase Generation
I-Stream Generator BHT Control Logic and BHT Array (Design under Test) Instruction Unit and Pipe Behavioral (checking and Driving BHT Array Loader BHT Array Shadow (Checking)
Automatic modification of random
parameters based on observed
coverage
Future Verification Trends
Integration of Simulation with Formal Verificatio
Logic
Description
Simulation Formal Verification Model Checking
Future Verification Trends
Sharing of verification I.P.
I/O I/O I/O I/O P P P P P P P P Memory P P P P P P P P Memory P P P P P P P P Memory P P P P P P P P Memory
anyServer
InfiniBand
Future Verification Trends
Sharing of verification I.P.
SOC Design will lead sharing of Verification IP Components come from multiple sources Need to supply verification IP Need to have standard backplane Need standard constructs