Hardware Interface - Microprocessor Based Systems - Lecture Slides, Slides of Microprocessor and Interfacing

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Lecture Overview

• The Hardware Interface

– The pins

– Special Characteristics of the ports

– Software control of I/O Port lines

• REF: Chapters 1,6, and 9 plus the 68HC

reference manual.

The hardware pins

• The hardware pins
  • Power and Ground
  • Timing
  • Interrupt
  • Port A – I/O lines (restricted in how used)
  • Port B – Output extended addressing
  • Port C – Bidirectional I/O
  • Port D – 5 bit port for serial I/O
  • Port E – 8 analog inputs

Port A

• The direction of Port A signal lines

– Note that

– 3 pins input

– 4 pins output

– 1 bidirectional

The I/O ports

• Port B – at address $

– An output port – has the dual use of being used

for external addressing when the MPU is

configured for extended memory mode.

• Port C – at address $

– All the lines are bidirectional

– The Port C data direction register DDRC is at

• This register configures the direction of the pins of the

port.

The ports

• Port D – only a 6 pin port - at $
  • Lines can be configured as general bidirectional I/O lines
  • The lines can be used for both asynchronous and

synchronous serial communication.

• The port is set up to implement a SPI – Serial Parallel

Interface

• SPI interface – allows communication with a peripheral or communication between processors in a multiple master MPU system.
• The SPI interface is one where data is simultaneously transmitted and received. It has two data lines MISO and MOSI for this.
• This is detailed in chapter 8 of the chip manual.
• Port D data direction register - $

Port D

• Port D can also be used to implement an

asynchronous serial interface sometimes referred

to as a UART system.

• The system implements a full duplex UART-type

system.

• Multiple control registers are use and can be

accessed.

• SCCR1 ($102C), SCCR2 ($102D), SCCR ($102E), SCDR ($102F), BAUD ($102B), SPCR ($1028), SPSR ($1029), SPDR ($102A)

Who is interrupting me?

• Interrupts are

generated either from

the two external pins,

IRQ and XIRQ or

internally from

various on chip

devices.

• The table lists the

interrupt sources on

the chip.

Handling an interrupt

• You need attention – your action? Raise your

hand

• A peripheral or internal device needs attention

• Generate an interrupt

• What needs to happen to service and interrupt

• Instruction executed in response to an interrupt are called the interrupt service routine
• Interrupt happen asynchronously
  • The current instruction will complete execution
  • All of the registers are saved on the stack

Getting to service routine

• After saving the state of the processor, the

next step is getting to the code of the correct

service routine.

• Program counter is loaded with the 2 bytes in

a interrupt vector table that is located at $FFxx

addresses.

• As these addresses are ROM, some systems

set these up such that they have value $00xx.

At these addresses is an unconditional jump,

JMP op code 7E, to the service routine.Docsity.com

Interrupt table

Interrupt action continued

• At that address, as shown previously, is a jump

instruction for an unconditional jump to the

interrupt service routine.

• When service routine completes it does so

with an RTI – Return from interrupt

instruction.

– As shown in the instruction action for the RTI

– The registers are restored

– Then the PC is restored to continue execution of

the interrupted program Docsity.com

Lecture summary

• Have looked at the ports of the 68HC

• Have looked at some specifics of 68HC

interrupt handling and interrupt handling in

general.