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Main points of this lecture are: Hashes, Addressing, Hardware Versus Software, Memory Addressing, Fragmentation, Allocation Patterns, Simple Memory Mapping, Page Tables, Logical Address, Caveats About Page Tables, Enter Virtual Memory, Hash Table
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Part architecture: what a modern processor can do Part tradition: we've always done it that way. Part performance: what works best. Today, we study how memory is managed "what you don't know, that can't kill you (but can kill your performance)" "CPU speed is a baldfaced lie." "gdb is a baldfaced lie." Goal: explain the mechanisms by which we achieve performance, and why we need them. Addressing Tuesday, November 02, 2010 1:21 PM Docsity.com
Features are built-in OS can't see them. But it has to manage them. Usually by responding to exceptional conditions (page faults, segmentation faults, and bus errors) In this lecture, most of what we are talking about is hardware. There are economic limits to what HW can do. Ex. virtual memory. Memory is homogeneous => can do in hardware. Disks are heterogeneous => it is prohibitively expensive to manage them in hardware => have to use software. But: a) generate an interrupt. b) call up OS. Do something non-generic: e.g., swap in a page from disk. c) d) return control to the process. We cope with missing hardware by: Recall: Hardware versus Software Tuesday, November 01, 2011 4:44 PM Docsity.com
logical pages map to physical frames addresses in the logical page correspond to physical frame addresses. So far, we have a very simple model of memory mapping pbase to pbound-1: page addresses fbase to fbound-1: frame addresses paddr: address offset in page faddr: address offset in frame paddr-pbase = faddr-fbase The address equation: faddr = (paddr-pbase) + fbase or Simple memory mapping Tuesday, November 02, 2010 12:14 PM Docsity.com
0xc Each logical address is separated into a page number and an offset A page table keeps track of the correspondence between pages and frames. Generalization of simple memory mapping Page tables Thursday, October 28, 2004 6:38 AM Docsity.com
The page table cache Tuesday, November 02, 2010 1:15 PM Docsity.com
Start with first segment needed in page cache. Add segments to page cache until it fills. Bump segments out of the cache via LRU. Use dirty bit to manage cache flush. How the OS intervenes The page cache is the physical load of the MMU. Underneath the hood: Everything is happy until a cache miss. a) interrupt the OS b) load a new cache entry. c) continue Then How it's done: How the OS intervenes Tuesday, November 01, 2011 4:55 PM Docsity.com
Picture of inverted page addressing Tuesday, November 02, 2010 1:33 PM Docsity.com
The hash is a correspondence with a virtual pointer pool The cache puts the hash in the processor when needed. Alas, we normally need both hashing and caching Hashing and caching Tuesday, November 02, 2010 1:39 PM Docsity.com
Page table : a simple idea: map logical to physical. Cached page table : a complex idea: allow a small thing to represent big structure. Page table hash : a simple idea: allow sparse maps. Cached page table hash : a complex idea: allow big sparse maps. When we started this discussion, I pointed out that simple semantics sometimes have complex implementations. Reason is speed. Simple semantics, complex implementation Tuesday, October 26, 2010 1:48 PM Docsity.com
○ A logical way of grouping a set of pages together. ○ Independent of paging scheme. ○ Intent: group pages by function, protection, sharing, etc. Segment descriptor table: encodes protections for segments.
○ An OS can use both page maps and segments. ○ Sometimes not supported by the processor. Book's example of segmentation without paging does not occur in practice.
Segmentation Segmentation Thursday, October 28, 2004 6:48 AM Docsity.com
One descriptor, multiple pages Setting read-only for a segment sets read-only for all of its pages. Simplify page descriptors, by moving attributes to segment descriptors. Why segments? Why segmentation? Tuesday, October 26, 2010 1:50 PM Docsity.com
Picture of segment addressing (basic) Tuesday, November 02, 2010 1:48 PM Docsity.com
array indexing cached arrays hashed arrays ("inverted indexing") cached hashed arrays and more… Note that in the previous diagram, I didn' t label how arrows are implemented. They can be: Implementing segments Implementing segments Tuesday, November 02, 2010 1:52 PM Docsity.com
You might think that these are all arrays. In fact, they're not. The reason for this is memory and table fragmentation. As processes use frames, they fragment frame space. This leads to fragmentation of the page maps. Which leads to fragmentation in segments. The key issue: fragmentation Tuesday, November 02, 2010 1:55 PM Docsity.com
